module cpu_datactrl(data_out,alu_out,fetch,mem_r,clk);  output [7:0] data_out;  reg[7:0] data_out;  input [7:0] alu_out;  input fetch,mem_r,clk;  always@(fetch or mem_r or posedge clk )    if(!fetch & !mem_r)       data_out=alu_out;    else      data_out=16'bz; endmodule