module cpu_counter(cnt_out,clk,data_in,reset,load);  input[12:0] data_in;  input clk,reset,load;  output [12:0] cnt_out;  reg [12:0] cnt_out;  always @( posedge clk or reset)     if(!reset)       cnt_out=13'b0;     else        if(load==1)          cnt_out=data_in;        else           if(cnt_out==5'b1000)//               cnt_out=13'b0;           else             cnt_out=cnt_out +1;   endmodule