library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newclk1 is
     port(clk:in std_logic;
      clr:in std_logic;
      clkc1_4:out std_logic;
      clrc1_4:out std_logic;
      start:out std_logic;
      
 counterTest:   out integer range 0 to 2052
      );
end newclk1;

architecture rtl of newclk1 is
signal counter:integer range 0 to 2052;
signal clkc1_4not:std_logic;
signal startnot:std_logic;
begin