+------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary    ;
+-----------------------------------+------------+
; Resource                          ; Usage      ;
+-----------------------------------+------------+
; Total logic elements              ; 33         ;
; Total combinational functions     ; 33         ;
;     -- Total 4-input functions    ; 8          ;
;     -- Total 3-input functions    ; 13         ;
;     -- Total 2-input functions    ; 0          ;
;     -- Total 1-input functions    ; 12         ;
;     -- Total 0-input functions    ; 0          ;
; Combinational cells for routing   ; 0          ;
; Total registers                   ; 12         ;
; Total logic cells in carry chains ; 12         ;
; I/O pins                          ; 22         ;
; Maximum fan-out node              ; counter[9] ;
; Maximum fan-out                   ; 12         ;
; Total fan-out                     ; 138        ;
; Average fan-out                   ; 2.51       ;
+-----------------------------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |newclk                    ; 33 (33)     ; 12           ; 0           ; 22   ; 0            ; 21 (21)      ; 0 (0)             ; 12 (12)          ; 12 (12)         ; |newclk             ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; clkc1not                                      ;   ;
; clkc2not                                      ;   ;
; clkc3not                                      ;   ;
; clkc4not                                      ;   ;
; clrc1$latch                                   ;   ;
; clrc2$latch                                   ;   ;
; clrc3$latch                                   ;   ;
; clrc4$latch                                   ;   ;
; Number of user-specified and inferred latches ; 8 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 12    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 12    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/mgh/mu/crc/crc.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat May 13 15:51:23 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off crc -c crc
Info: Found 1 design units, including 1 entities, in source file crcsend.bdf
    Info: Found entity 1: crcsend
Info: Found 2 design units, including 1 entities, in source file newclk.vhd
    Info: Found design unit 1: newclk-rtl
    Info: Found entity 1: newclk
Info: Found 2 design units, including 1 entities, in source file newclk1.vhd
    Info: Found design unit 1: newclk1-rtl
    Info: Found entity 1: newclk1
Info: Elaborating entity "newclk" for the top level hierarchy
Warning: VHDL Process Statement warning at newclk.vhd(43): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(53): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(56): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(59): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(62): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(65): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(68): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(71): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(74): signal "counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clkc1not" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clkc1not" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clkc2not" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clkc2not" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clkc3not" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clkc3not" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clkc4not" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clkc4not" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clrc1" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clrc1" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clrc2" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clrc2" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clrc3" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clrc3" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at newclk.vhd(34): signal or variable "clrc4" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "clrc4" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Implemented 55 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 20 output pins
    Info: Implemented 33 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 17 warnings
    Info: Processing ended: Sat May 13 15:51:25 2006
    Info: Elapsed time: 00:00:03