?? newclk.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity newclk is
port(clk:in std_logic;
start:in std_logic;
clkc1:out std_logic;
clkc2:out std_logic;
clkc3:out std_logic;
clkc4:out std_logic;
clrc1:out std_logic;
clrc2:out std_logic;
clrc3:out std_logic;
clrc4:out std_logic;
counterTest: out integer range 0 to 2052
);
end newclk;
architecture rtl of newclk is
signal counter:integer range 0 to 2052;
signal clkc1not:std_logic;
signal clkc2not:std_logic;
signal clkc3not:std_logic;
signal clkc4not:std_logic;
begin
process(clk,start)
begin
if(start='1') then
counter<=0;
elsif(clk'event and clk='1')then
counter<=counter+1;
end if;
if(counter=0) then
clkc1not<='1';
clkc2not<='1';
clkc3not<='1';
clkc4not<='1';
clrc1<='1';
clrc2<='1';
clrc3<='1';
clrc4<='1';
else
if(counter=1) then
clkc1not<='0';
end if;
if(counter=513) then
clkc2not<='0';
end if;
if(counter=1025) then
clkc3not<='0';
end if;
if(counter=1537) then
clkc4not<='0';
end if;
if(counter=2) then
clrc1<='0';
end if;
if(counter=514) then
clrc2<='0';
end if;
if(counter=1026) then
clrc3<='0';
end if;
if(counter=1538) then
clrc4<='0';
end if;
end if;
end process;
counterTest<=counter;
clkc1<=not clkc1not;
clkc2<=not clkc2not;
clkc3<=not clkc3not;
clkc4<=not clkc4not;
end rtl;
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