{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "F_IN " "Info: Assuming node \"F_IN\" is an undefined clock" {  } { { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 63 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "F_IN" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "F_IN register lpm_counter:Q0_rtl_0\|dffs\[0\] register F_OUT~reg0 140.85 MHz 7.1 ns Internal " "Info: Clock \"F_IN\" has Internal fmax of 140.85 MHz between source register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" and destination register \"F_OUT~reg0\" (period= 7.1 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.800 ns + Longest register register " "Info: + Longest register to register delay is 4.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 1 REG LC67 45 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "" { lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.800 ns) 4.800 ns F_OUT~reg0 2 REG LC9 1 " "Info: 2: + IC(2.000 ns) + CELL(2.800 ns) = 4.800 ns; Loc. = LC9; Fanout = 1; REG Node = 'F_OUT~reg0'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] F_OUT~reg0 } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 58.33 % " "Info: Total cell delay = 2.800 ns ( 58.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 41.67 % " "Info: Total interconnect delay = 2.000 ns ( 41.67 % )" {  } {  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] F_OUT~reg0 } { 0.000ns 2.000ns } { 0.000ns 2.800ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"F_IN\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "" { F_IN } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns F_OUT~reg0 2 REG LC9 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC9; Fanout = 1; REG Node = 'F_OUT~reg0'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "0.400 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out F_OUT~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"F_IN\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "" { F_IN } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out F_OUT~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 127 -1 0 } }  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.800 ns" { lpm_counter:Q0_rtl_0|dffs[0] F_OUT~reg0 } { 0.000ns 2.000ns } { 0.000ns 2.800ns } } } { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN F_OUT~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out F_OUT~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:Q0_rtl_0\|dffs\[0\] CLR F_IN 3.800 ns register " "Info: tsu for register \"lpm_counter:Q0_rtl_0\|dffs\[0\]\" (data pin = \"CLR\", clock pin = \"F_IN\") is 3.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.000 ns + Longest pin register " "Info: + Longest pin to register delay is 5.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns CLR 1 PIN PIN_81 57 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 57; PIN Node = 'CLR'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "" { CLR } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 62 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(2.800 ns) 5.000 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(2.000 ns) + CELL(2.800 ns) = 5.000 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "4.800 ns" { CLR lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 60.00 % " "Info: Total cell delay = 3.000 ns ( 60.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 40.00 % " "Info: Total interconnect delay = 2.000 ns ( 40.00 % )" {  } {  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "5.000 ns" { CLR lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { CLR CLR~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "F_IN destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"F_IN\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns F_IN 1 CLK PIN_83 25 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 25; CLK Node = 'F_IN'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "" { F_IN } "NODE_NAME" } "" } } { "counter.v" "" { Text "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/counter.v" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Q0_rtl_0\|dffs\[0\] 2 REG LC67 45 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC67; Fanout = 45; REG Node = 'lpm_counter:Q0_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "0.400 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "5.000 ns" { CLR lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.000 ns" { CLR CLR~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 0.200ns 2.800ns } } } { "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" "" { Report "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter_cmp.qrpt" Compiler "counter" "UNKNOWN" "V1" "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/db/counter.quartus_db" { Floorplan "E:/戴仙金/書/Verilog書/源代碼/cymometer/counter/" "" "2.200 ns" { F_IN lpm_counter:Q0_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { F_IN F_IN~out lpm_counter:Q0_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0}