?? gate_control.map.rpt
字號:
Analysis & Synthesis report for gate_control
Mon Jul 17 20:29:14 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. User-Specified and Inferred Latches
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Source Files Read
9. Analysis & Synthesis Resource Usage Summary
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Jul 17 20:29:14 2006 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; gate_control ;
; Top-level Entity Name ; gate_control ;
; Family ; MAX7000S ;
; Total macrocells ; 9 ;
; Total pins ; 12 ;
+-----------------------------+------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+--------------+---------------+
; Family name ; MAX7000S ; Stratix ;
; Use smart compilation ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; gate_control ; gate_control ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Auto Logic Cell Insertion ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Parallel Expanders ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A ; 100 ; 100 ;
+----------------------------------------------------------------------+--------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
gate_control
+---------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+---+
; Latch Name ; ;
+-----------------------------------------------+---+
; dp_s1hz$latch ; ;
; dp_s10hz$latch ; ;
; dp_s100hz$latch ; ;
; fref ; ;
; Number of user-specified and inferred latches ; 4 ;
+-----------------------------------------------+---+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+---------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------+------------+------+---------------------+
; |gate_control ; 9 ; 12 ; |gate_control ;
+----------------------------+------------+------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/戴仙金/資料/Verilog書/源代碼/cymometer/gate_control/gate_control.map.eqn.
+----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------------------------------------------------------------+
; gate_control.v ; yes ; E:/戴仙金/資料/Verilog書/源代碼/cymometer/gate_control/gate_control.v ;
+----------------------------------+-----------------+-----------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 9 ;
; Total registers ; 2 ;
; I/O pins ; 12 ;
; Shareable expanders ; 1 ;
; Maximum fan-out node ; SW1 ;
; Maximum fan-out ; 6 ;
; Total fan-out ; 41 ;
; Average fan-out ; 1.86 ;
+----------------------+----------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Mon Jul 17 20:29:12 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off gate_control -c gate_control
Info: Found 1 design units, including 1 entities, in source file gate_control.v
Info: Found entity 1: gate_control
Warning: Verilog HDL unsupported feature warning at gate_control.v(30): Initial Construct is not supported and will be ignored
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable fref may not be assigned a new value in every possible path through the Always Construct. Variable fref holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable dp_s1hz may not be assigned a new value in every possible path through the Always Construct. Variable dp_s1hz holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable dp_s10hz may not be assigned a new value in every possible path through the Always Construct. Variable dp_s10hz holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Verilog HDL Always Construct warning at gate_control.v(34): variable dp_s100hz may not be assigned a new value in every possible path through the Always Construct. Variable dp_s100hz holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Implemented 22 device resources after synthesis - the final resource count might be different
Info: Implemented 6 input pins
Info: Implemented 6 output pins
Info: Implemented 9 macrocells
Info: Implemented 1 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Mon Jul 17 20:29:14 2006
Info: Elapsed time: 00:00:04