?? gate_control.tan.rpt
字號:
Timing Analyzer report for gate_control
Mon Jul 17 20:29:32 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'SW2'
6. Clock Setup: 'f100hz'
7. Clock Setup: 'SW1'
8. Clock Setup: 'f10hz'
9. Clock Setup: 'f1hz'
10. Clock Setup: 'SW0'
11. Clock Hold: 'SW2'
12. Clock Hold: 'SW1'
13. tco
14. tpd
15. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------+----------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 23.800 ns ; wire_2 ; Latch_EN ; SW1 ; ; 0 ;
; Worst-case tpd ; N/A ; None ; 8.100 ns ; SW0 ; dp_s1hz ; ; ; 0 ;
; Clock Setup: 'SW1' ; N/A ; None ; 33.56 MHz ( period = 29.800 ns ) ; wire_1 ; wire_2 ; SW1 ; SW1 ; 0 ;
; Clock Setup: 'SW2' ; N/A ; None ; 48.54 MHz ( period = 20.600 ns ) ; wire_1 ; wire_2 ; SW2 ; SW2 ; 0 ;
; Clock Setup: 'SW0' ; N/A ; None ; 56.82 MHz ( period = 17.600 ns ) ; wire_1 ; wire_2 ; SW0 ; SW0 ; 0 ;
; Clock Setup: 'f1hz' ; N/A ; None ; 87.72 MHz ( period = 11.400 ns ) ; wire_1 ; wire_2 ; f1hz ; f1hz ; 0 ;
; Clock Setup: 'f10hz' ; N/A ; None ; 87.72 MHz ( period = 11.400 ns ) ; wire_1 ; wire_2 ; f10hz ; f10hz ; 0 ;
; Clock Setup: 'f100hz' ; N/A ; None ; 87.72 MHz ( period = 11.400 ns ) ; wire_1 ; wire_2 ; f100hz ; f100hz ; 0 ;
; Clock Hold: 'SW1' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; wire_1 ; wire_2 ; SW1 ; SW1 ; 2 ;
; Clock Hold: 'SW2' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; wire_1 ; wire_2 ; SW2 ; SW2 ; 2 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 4 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM7032SLC44-5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minumum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Clock Analysis Only ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off clear and preset signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Do Min/Max analysis using Rise/Fall delays ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Use Clock Latency for PLL offset ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; SW2 ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; f100hz ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; SW1 ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; f10hz ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; f1hz ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; SW0 ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW2' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 48.54 MHz ( period = 20.600 ns ) ; wire_1 ; wire_2 ; SW2 ; SW2 ; None ; None ; 3.600 ns ;
; N/A ; 97.09 MHz ( period = 10.300 ns ) ; wire_1 ; wire_1 ; SW2 ; SW2 ; None ; None ; 3.600 ns ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'f100hz' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 87.72 MHz ( period = 11.400 ns ) ; wire_1 ; wire_2 ; f100hz ; f100hz ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; wire_1 ; wire_1 ; f100hz ; f100hz ; None ; None ; 3.600 ns ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW1' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 33.56 MHz ( period = 29.800 ns ) ; wire_1 ; wire_2 ; SW1 ; SW1 ; None ; None ; 3.600 ns ;
; N/A ; 67.11 MHz ( period = 14.900 ns ) ; wire_1 ; wire_1 ; SW1 ; SW1 ; None ; None ; 3.600 ns ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'f10hz' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 87.72 MHz ( period = 11.400 ns ) ; wire_1 ; wire_2 ; f10hz ; f10hz ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; wire_1 ; wire_1 ; f10hz ; f10hz ; None ; None ; 3.600 ns ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'f1hz' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 87.72 MHz ( period = 11.400 ns ) ; wire_1 ; wire_2 ; f1hz ; f1hz ; None ; None ; 3.600 ns ;
; N/A ; 175.44 MHz ( period = 5.700 ns ) ; wire_1 ; wire_1 ; f1hz ; f1hz ; None ; None ; 3.600 ns ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'SW0' ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; wire_1 ; wire_2 ; SW0 ; SW0 ; None ; None ; 3.600 ns ;
; N/A ; 113.64 MHz ( period = 8.800 ns ) ; wire_1 ; wire_1 ; SW0 ; SW0 ; None ; None ; 3.600 ns ;
+-------+----------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+
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