; N/A   ; None         ; 2.900 ns   ; A0[2] ; Q0[2]~reg0 ; clk      ;
+-------+--------------+------------+-------+------------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 3.200 ns   ; Q5[0]~reg0 ; Q5[0] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q5[1]~reg0 ; Q5[1] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q5[2]~reg0 ; Q5[2] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q5[3]~reg0 ; Q5[3] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q4[0]~reg0 ; Q4[0] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q4[1]~reg0 ; Q4[1] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q4[2]~reg0 ; Q4[2] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q4[3]~reg0 ; Q4[3] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q3[0]~reg0 ; Q3[0] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q3[1]~reg0 ; Q3[1] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q3[2]~reg0 ; Q3[2] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q3[3]~reg0 ; Q3[3] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q2[0]~reg0 ; Q2[0] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q2[1]~reg0 ; Q2[1] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q2[2]~reg0 ; Q2[2] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q2[3]~reg0 ; Q2[3] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q1[0]~reg0 ; Q1[0] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q1[1]~reg0 ; Q1[1] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q1[2]~reg0 ; Q1[2] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q1[3]~reg0 ; Q1[3] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q0[0]~reg0 ; Q0[0] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q0[1]~reg0 ; Q0[1] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q0[2]~reg0 ; Q0[2] ; clk        ;
; N/A   ; None         ; 3.200 ns   ; Q0[3]~reg0 ; Q0[3] ; clk        ;
+-------+--------------+------------+------------+-------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+-------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To         ; To Clock ;
+---------------+-------------+-----------+-------+------------+----------+
; N/A           ; None        ; -0.400 ns ; A0[3] ; Q0[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A5[0] ; Q5[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A5[1] ; Q5[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A5[2] ; Q5[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A5[3] ; Q5[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A4[0] ; Q4[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A4[1] ; Q4[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A4[2] ; Q4[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A4[3] ; Q4[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A3[0] ; Q3[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A3[1] ; Q3[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A3[2] ; Q3[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A3[3] ; Q3[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A2[0] ; Q2[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A2[1] ; Q2[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A2[2] ; Q2[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A2[3] ; Q2[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A1[0] ; Q1[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A1[1] ; Q1[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A1[2] ; Q1[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A1[3] ; Q1[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A0[0] ; Q0[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A0[1] ; Q0[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.400 ns ; A0[2] ; Q0[2]~reg0 ; clk      ;
+---------------+-------------+-----------+-------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Mon Jul 10 20:57:09 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off flip_latch -c flip_latch
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "Q0[3]~reg0" (data pin = "A0[3]", clock pin = "clk") is 2.900 ns
    Info: + Longest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'A0[3]'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0[3]~reg0'
        Info: Total cell delay = 2.800 ns ( 71.79 % )
        Info: Total interconnect delay = 1.100 ns ( 28.21 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "clk" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0[3]~reg0'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "Q5[0]" through register "Q5[0]~reg0" is 3.200 ns
    Info: + Longest clock path from clock "clk" to source register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC17; Fanout = 1; REG Node = 'Q5[0]~reg0'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.200 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 1; REG Node = 'Q5[0]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_37; Fanout = 0; PIN Node = 'Q5[0]'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "Q0[3]~reg0" (data pin = "A0[3]", clock pin = "clk") is -0.400 ns
    Info: + Longest clock path from clock "clk" to destination register is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_87; Fanout = 24; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 1.800 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0[3]~reg0'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_84; Fanout = 1; PIN Node = 'A0[3]'
        Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.900 ns; Loc. = LC1; Fanout = 1; REG Node = 'Q0[3]~reg0'
        Info: Total cell delay = 2.800 ns ( 71.79 % )
        Info: Total interconnect delay = 1.100 ns ( 28.21 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jul 10 20:57:09 2006
    Info: Elapsed time: 00:00:01