?? fdiv.tan.qmsg
字號:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_8MHz " "Info: Assuming node \"Clock_8MHz\" is an undefined clock" { } { { "fdiv.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.v" 10 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_8MHz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_8MHz register lpm_counter:CNT_rtl_0\|dffs\[0\] register lpm_counter:CNT_rtl_0\|dffs\[3\] 175.44 MHz 5.7 ns Internal " "Info: Clock \"Clock_8MHz\" has Internal fmax of 175.44 MHz between source register \"lpm_counter:CNT_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:CNT_rtl_0\|dffs\[3\]\" (period= 5.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.600 ns + Longest register register " "Info: + Longest register to register delay is 3.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:CNT_rtl_0\|dffs\[0\] 1 REG LC3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "" { lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.600 ns lpm_counter:CNT_rtl_0\|dffs\[3\] 2 REG LC1 3 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 3; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "3.600 ns" { lpm_counter:CNT_rtl_0|dffs[0] lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 72.22 % " "Info: Total cell delay = 2.600 ns ( 72.22 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 27.78 % " "Info: Total interconnect delay = 1.000 ns ( 27.78 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "3.600 ns" { lpm_counter:CNT_rtl_0|dffs[0] lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:CNT_rtl_0|dffs[0] lpm_counter:CNT_rtl_0|dffs[3] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_8MHz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_8MHz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:CNT_rtl_0\|dffs\[3\] 2 REG LC1 3 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 3; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[3\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "0.100 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"Clock_8MHz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_8MHz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:CNT_rtl_0\|dffs\[0\] 2 REG LC3 5 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "0.100 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "3.600 ns" { lpm_counter:CNT_rtl_0|dffs[0] lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.600 ns" { lpm_counter:CNT_rtl_0|dffs[0] lpm_counter:CNT_rtl_0|dffs[3] } { 0.000ns 1.000ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[3] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[3] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:CNT_rtl_0\|dffs\[0\] Reset Clock_8MHz 3.300 ns register " "Info: tsu for register \"lpm_counter:CNT_rtl_0\|dffs\[0\]\" (data pin = \"Reset\", clock pin = \"Clock_8MHz\") is 3.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.800 ns + Longest pin register " "Info: + Longest pin to register delay is 3.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Reset 1 PIN PIN_24 7 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'Reset'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "" { Reset } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.v" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.600 ns) 3.800 ns lpm_counter:CNT_rtl_0\|dffs\[0\] 2 REG LC3 5 " "Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "3.600 ns" { Reset lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 73.68 % " "Info: Total cell delay = 2.800 ns ( 73.68 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 26.32 % " "Info: Total interconnect delay = 1.000 ns ( 26.32 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "3.800 ns" { Reset lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { Reset Reset~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_8MHz destination 1.300 ns - Shortest register " "Info: - Shortest clock path from clock \"Clock_8MHz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_8MHz 1 CLK PIN_43 4 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 4; CLK Node = 'Clock_8MHz'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "" { Clock_8MHz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:CNT_rtl_0\|dffs\[0\] 2 REG LC3 5 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC3; Fanout = 5; REG Node = 'lpm_counter:CNT_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "0.100 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "3.800 ns" { Reset lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.800 ns" { Reset Reset~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.000ns } { 0.000ns 0.200ns 2.600ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv_cmp.qrpt" Compiler "fdiv" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/db/fdiv.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/" "" "1.300 ns" { Clock_8MHz lpm_counter:CNT_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_8MHz Clock_8MHz~out lpm_counter:CNT_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
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