?? fdiv.fit.rpt
字號:
Fitter report for fdiv
Wed Jul 19 20:30:56 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Pin-Out File
7. Fitter Resource Usage Summary
8. Input Pins
9. Output Pins
10. All Package Pins
11. I/O Standard
12. Dedicated Inputs I/O
13. Output Pin Default Load For Reported TCO
14. Fitter Resource Utilization by Entity
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Interconnect Usage Summary
19. LAB Macrocells
20. Logic Cell Interconnection
21. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Wed Jul 19 20:30:56 2006 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; fdiv ;
; Top-level Entity Name ; fdiv ;
; Family ; MAX7000S ;
; Device ; EPM7032SLC44-5 ;
; Timing Models ; Final ;
; Total macrocells ; 4 / 32 ( 12 % ) ;
; Total pins ; 8 / 36 ( 22 % ) ;
+-----------------------+------------------------------------------+
+--------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------+--------------------+--------------------+
; Device ; AUTO ; ;
; Use smart compilation ; Normal ; Normal ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
+--------------------------------------------+--------------------+--------------------+
+----------------------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+-----------------------------------------+
; Option ; Setting ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving an unspecified signal ;
; Security bit ; Off ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+-----------------------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.fit.eqn.
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/戴仙金/資料/Verilog書/源代碼/step_motor/fdiv/fdiv.pin.
+---------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-------------------------------+-------------------------------+
; Resource ; Usage ;
+-------------------------------+-------------------------------+
; Logic cells ; 4 / 32 ( 12 % ) ;
; Registers ; 4 / 32 ( 12 % ) ;
; Number of pterms used ; 7 ;
; User inserted logic elements ; 0 ;
; I/O pins ; 8 / 36 ( 22 % ) ;
; -- Clock pins ; 1 / 2 ( 50 % ) ;
; -- Dedicated input pins ; 0 / 2 ( 0 % ) ;
; Global signals ; 1 ;
; Shareable expanders ; 0 / 32 ( 0 % ) ;
; Parallel expanders ; 0 / 30 ( 0 % ) ;
; Cells using turbo bit ; 4 / 32 ( 12 % ) ;
; Maximum fan-out node ; lpm_counter:CNT_rtl_0|dffs[0] ;
; Maximum fan-out ; 4 ;
; Total fan-out ; 20 ;
; Average fan-out ; 1.67 ;
+-------------------------------+-------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Clock_8MHz ; 43 ; -- ; -- ; 4 ; 0 ; yes ; no ; TTL ; Fitter ;
; Reset ; 24 ; -- ; 2 ; 4 ; 0 ; no ; no ; TTL ; Fitter ;
+------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+-----------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+
; Name ; Pin # ; I/O Bank ; LAB ; Output Register ; Slow Slew Rate ; Open Drain ; TRI Primitive ; I/O Standard ; Location assigned by ;
+-----------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+
; F_1Hz ; 4 ; -- ; 1 ; no ; no ; no ; no ; TTL ; Fitter ;
; F_65536Hz ; 5 ; -- ; 1 ; no ; no ; no ; no ; TTL ; Fitter ;
+-----------+-------+----------+-----+-----------------+----------------+------------+---------------+--------------+----------------------+
+-------------------------------------------------------------------------------------------------------+
; All Package Pins ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; User Assignment ;
+----------+------------+----------+----------------+--------+--------------+---------+-----------------+
; 1 ; 0 ; -- ; GND+ ; ; ; ; ;
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