Fitter report for pulse_16
Wed Jul 19 21:11:40 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. All Package Pins
 11. Output Pin Default Load For Reported TCO
 12. Fitter Resource Utilization by Entity
 13. Non-Global High Fan-Out Signals
 14. Interconnect Usage Summary
 15. LAB Macrocells
 16. Logic Cell Interconnection
 17. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+------------------------------------------------------------------+
; Fitter Summary                                                   ;
+-----------------------+------------------------------------------+
; Fitter Status         ; Successful - Wed Jul 19 21:11:40 2006    ;
; Quartus II Version    ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name         ; pulse_16                                 ;
; Top-level Entity Name ; pulse_16                                 ;
; Family                ; MAX7000S                                 ;
; Device                ; EPM7064STC100-5                          ;
; Timing Models         ; Final                                    ;
; Total macrocells      ; 16 / 64 ( 25 % )                         ;
; Total pins            ; 37 / 68 ( 54 % )                         ;
+-----------------------+------------------------------------------+


+--------------------------------------------------------------------------------------+
; Fitter Settings                                                                      ;
+--------------------------------------------+--------------------+--------------------+
; Option                                     ; Setting            ; Default Value      ;
+--------------------------------------------+--------------------+--------------------+
; Device                                     ; AUTO               ;                    ;
; Use smart compilation                      ; Normal             ; Normal             ;
; Optimize Timing                            ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On                 ; On                 ;
; Limit to One Fitting Attempt               ; Off                ; Off                ;
; Fitter Initial Placement Seed              ; 1                  ; 1                  ;
; Slow Slew Rate                             ; Off                ; Off                ;
; Fitter Effort                              ; Auto Fit           ; Auto Fit           ;
+--------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;
+----------------------------------------------+-----------------------------------------+
; Option                                       ; Setting                                 ;
+----------------------------------------------+-----------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                                     ;
; Enable device-wide reset (DEV_CLRn)          ; Off                                     ;
; Enable device-wide output enable (DEV_OE)    ; Off                                     ;
; Enable INIT_DONE output                      ; Off                                     ;
; Configuration scheme                         ; Passive Serial                          ;
; Reserve all unused pins                      ; As output driving an unspecified signal ;
; Security bit                                 ; Off                                     ;
; Base pin-out file on sameframe device        ; Off                                     ;
+----------------------------------------------+-----------------------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/戴仙金/資料/Verilog書/源代碼/step_motor/pulse_16/pulse_16.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/戴仙金/資料/Verilog書/源代碼/step_motor/pulse_16/pulse_16.pin.


+--------------------------------------------------+
; Fitter Resource Usage Summary                    ;
+-------------------------------+------------------+
; Resource                      ; Usage            ;
+-------------------------------+------------------+
; Logic cells                   ; 16 / 64 ( 25 % ) ;
; Registers                     ; 0 / 64 ( 0 % )   ;
; Number of pterms used         ; 16               ;
; User inserted logic elements  ; 0                ;
; I/O pins                      ; 37 / 68 ( 54 % ) ;
;     -- Clock pins             ; 0 / 2 ( 0 % )    ;
;     -- Dedicated input pins   ; 0 / 2 ( 0 % )    ;
; Global signals                ; 0                ;
; Shareable expanders           ; 0 / 64 ( 0 % )   ;
; Parallel expanders            ; 0 / 60 ( 0 % )   ;
; Cells using turbo bit         ; 16 / 64 ( 25 % ) ;
; Maximum fan-out node          ; Reset            ;
; Maximum fan-out               ; 16               ;
; Total fan-out                 ; 168              ;
; Average fan-out               ; 3.17             ;
+-------------------------------+------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                             ;
+------------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Name             ; Pin # ; I/O Bank ; LAB ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; I/O Standard ; Location assigned by ;
+------------------+-------+----------+-----+-----------------------+--------------------+--------+----------------+--------------+----------------------+
; Reset            ; 84    ; --       ; 4   ; 16                    ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; counter_data[0]  ; 85    ; --       ; 4   ; 16                    ; 0                  ; no     ; no             ; TTL          ; Fitter               ;
; counter_data[10] ; 46    ; --       ; 3   ; 6                     ; 0                  ; no     ; no             ; TTL          ; Fitter               ;