?? pulse_16.sim.vwf

?? 采用Verilog HDL語言編寫的步進電機位置系統
?? VWF
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}

TRANSITION_LIST("counter_data[0]")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 50;
			LEVEL 0 FOR 10.0;
			LEVEL 1 FOR 10.0;
		}
	}
}

TRANSITION_LIST("pulse_16_out[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 15.1;
		NODE
		{
			REPEAT = 49;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 10.0;
		}
		LEVEL 1 FOR 4.9;
	}
}

TRANSITION_LIST("pulse_16_out[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 25.1;
		NODE
		{
			REPEAT = 24;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 30.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 4.9;
	}
}

TRANSITION_LIST("pulse_16_out[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 45.1;
		NODE
		{
			REPEAT = 11;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 70.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 64.9;
	}
}

TRANSITION_LIST("pulse_16_out[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 85.1;
		NODE
		{
			REPEAT = 5;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 150.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 104.9;
	}
}

TRANSITION_LIST("pulse_16_out[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 165.1;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 310.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 184.9;
	}
}

TRANSITION_LIST("pulse_16_out[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 325.1;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 630.0;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 24.9;
	}
}

TRANSITION_LIST("pulse_16_out[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 645.1;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 344.9;
	}
}

TRANSITION_LIST("pulse_16_out[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("pulse_16_out[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "Reset";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 1;
	TREE_LEVEL = 0;
	CHILDREN = 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "counter_data[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 1;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out";
	EXPAND_STATUS = EXPANDED;
	RADIX = Hexadecimal;
	TREE_INDEX = 18;
	TREE_LEVEL = 0;
	CHILDREN = 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 33;
	TREE_LEVEL = 1;
	PARENT = 18;
}

DISPLAY_LINE
{
	CHANNEL = "pulse_16_out[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 34;
	TREE_LEVEL = 1;
	PARENT = 18;
}

TIME_BAR
{
	TIME = 10050;
	MASTER = TRUE;
}
;
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?? 文件大小 1435 K
?? 上傳用戶 ATT320
?? 所屬分類 VHDL/FPGA/Verilog
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?? pulse_16.sim.vwf

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