?? counter_16_bits.v
字號:
module counter_16_bits(
Clk_65536Hz,
Reset,
counter_out);
output [15:0] counter_out;
input Clk_65536Hz;
input Reset;
reg [15:0] counter_out;
always @(posedge Clk_65536Hz)
begin
if(counter_out < 16'b1111111111111111)
counter_out <= counter_out + 16'b1;
else
counter_out <= 16'b0;
end
endmodule
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