?? main.map.rpt
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Analysis & Synthesis report for main
Wed Aug 02 16:41:20 2006
Version 4.2 Build 157 12/07/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Hierarchy
5. User-Specified and Inferred Latches
6. General Register Statistics
7. WYSIWYG Cells
8. Analysis & Synthesis Resource Utilization by Entity
9. Analysis & Synthesis Equations
10. Analysis & Synthesis Source Files Read
11. Analysis & Synthesis Resource Usage Summary
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Aug 02 16:41:20 2006 ;
; Quartus II Version ; 4.2 Build 157 12/07/2004 SJ Full Version ;
; Revision Name ; main ;
; Top-level Entity Name ; main ;
; Family ; ACEX1K ;
; Total logic elements ; 212 ;
; Total pins ; 60 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------+--------------+---------------+
; Family name ; ACEX1K ; Stratix ;
; Use smart compilation ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; main ; main ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
+------------------------------------------------------+--------------+---------------+
+-----------+
; Hierarchy ;
+-----------+
main
|-- fdiv:inst
|-- lpm_counter:CNT_rtl_1
|-- alt_counter_f10ke:wysi_counter
|-- counter_16_bits:inst1
|-- lpm_counter:counter_out_rtl_2
|-- alt_counter_f10ke:wysi_counter
|-- pulse_16:inst2
|-- second_pulse_latch:inst3
|-- lpm_add_sub:add_rtl_4
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:add_rtl_5
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- pulse_sum:inst4
|-- sum_control:inst5
|-- lpm_add_sub:add_rtl_3
|-- addcore:adder
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_counter:step_counter_rtl_0
|-- alt_counter_f10ke:wysi_counter
+----------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------+----+
; Latch Name ; ;
+-----------------------------------------------+----+
; pulse_sum:inst4|pulse_1[14] ; ;
; pulse_sum:inst4|pulse_1[13] ; ;
; pulse_sum:inst4|pulse_1[12] ; ;
; pulse_sum:inst4|pulse_1[11] ; ;
; pulse_sum:inst4|pulse_1[10] ; ;
; pulse_sum:inst4|pulse_1[9] ; ;
; pulse_sum:inst4|pulse_1[8] ; ;
; pulse_sum:inst4|pulse_1[7] ; ;
; pulse_sum:inst4|pulse_1[6] ; ;
; pulse_sum:inst4|pulse_1[5] ; ;
; pulse_sum:inst4|pulse_1[4] ; ;
; pulse_sum:inst4|pulse_1[3] ; ;
; pulse_sum:inst4|pulse_1[2] ; ;
; pulse_sum:inst4|pulse_1[1] ; ;
; pulse_sum:inst4|pulse_1[0] ; ;
; Number of user-specified and inferred latches ; 15 ;
+-----------------------------------------------+----+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 79 ;
; Number of registers using Synchronous Clear ; 63 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 24 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
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