{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Adc_SCL " "Info: Assuming node \"Adc_SCL\" is an undefined clock" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Adc_SCL" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "Adc_SCL register register lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] Data\[5\] 250.0 MHz Internal " "Info: Clock \"Adc_SCL\" Internal fmax is restricted to 250.0 MHz between source register \"lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination register \"Data\[5\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.0 ns 2.0 ns 4.0 ns " "Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register register " "Info: + Longest register to register delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC4_B3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_B3; Fanout = 15; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(1.100 ns) 1.600 ns Decoder~22 2 COMB LC1_B4 1 " "Info: 2: + IC(0.500 ns) + CELL(1.100 ns) = 1.600 ns; Loc. = LC1_B4; Fanout = 1; COMB Node = 'Decoder~22'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.600 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Decoder~22 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.600 ns) 2.300 ns Data\[5\] 3 REG LC5_B4 1 " "Info: 3: + IC(0.100 ns) + CELL(0.600 ns) = 2.300 ns; Loc. = LC5_B4; Fanout = 1; REG Node = 'Data\[5\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.700 ns" { Decoder~22 Data[5] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 73.91 % " "Info: Total cell delay = 1.700 ns ( 73.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 26.09 % " "Info: Total interconnect delay = 0.600 ns ( 26.09 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "2.300 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Decoder~22 Data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.300 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Decoder~22 Data[5] } { 0.000ns 0.500ns 0.100ns } { 0.000ns 1.100ns 0.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Adc_SCL destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock \"Adc_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_SCL 1 CLK PIN_39 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 19; CLK Node = 'Adc_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_SCL } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Data\[5\] 2 REG LC5_B4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC5_B4; Fanout = 1; REG Node = 'Data\[5\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.200 ns" { Adc_SCL Data[5] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[5] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Adc_SCL source 1.500 ns - Longest register " "Info: - Longest clock path from clock \"Adc_SCL\" to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_SCL 1 CLK PIN_39 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 19; CLK Node = 'Adc_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_SCL } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC4_B3 15 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_B3; Fanout = 15; REG Node = 'lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.200 ns" { Adc_SCL lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[5] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "2.300 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Decoder~22 Data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.300 ns" { lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Decoder~22 Data[5] } { 0.000ns 0.500ns 0.100ns } { 0.000ns 1.100ns 0.600ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[5] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Data[5] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { Data[5] } {  } {  } } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "Data\[15\] Adc_Sdata Adc_SCL 0.600 ns register " "Info: tsu for register \"Data\[15\]\" (data pin = \"Adc_Sdata\", clock pin = \"Adc_SCL\") is 0.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest pin register " "Info: + Longest pin to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_Sdata 1 PIN PIN_91 12 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 12; PIN Node = 'Adc_Sdata'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_Sdata } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 1.700 ns Data\[15\] 2 REG LC4_B2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 1.700 ns; Loc. = LC4_B2; Fanout = 1; REG Node = 'Data\[15\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.400 ns" { Adc_Sdata Data[15] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 100.00 % " "Info: Total cell delay = 1.700 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.700 ns" { Adc_Sdata Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.700 ns" { Adc_Sdata Adc_Sdata~out Data[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Adc_SCL destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Adc_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Adc_SCL 1 CLK PIN_39 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 19; CLK Node = 'Adc_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "" { Adc_SCL } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Data\[15\] 2 REG LC4_B2 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_B2; Fanout = 1; REG Node = 'Data\[15\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "0.200 ns" { Adc_SCL Data[15] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[15] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.700 ns" { Adc_Sdata Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.700 ns" { Adc_Sdata Adc_Sdata~out Data[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.300ns 0.400ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read_cmp.qrpt" Compiler "Data_Read" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/db/Data_Read.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/Data_Read/" "" "1.500 ns" { Adc_SCL Data[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Adc_SCL Adc_SCL~out Data[15] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } }  } 0}