?? main.map.qmsg
字號:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 04 17:49:46 2006 " "Info: Processing started: Fri Aug 04 17:49:46 2006" { } { } 0} } { } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off main -c main --convert_bdf_to_verilog=main.bdf " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off main -c main --convert_bdf_to_verilog=main.bdf" { } { } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 main " "Info: Found entity 1: main" { } { { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { } } } } 0} } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 04 17:49:46 2006 " "Info: Processing ended: Fri Aug 04 17:49:46 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { }
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