?? main.tan.qmsg
字號:
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] Clk_SCL 1.2 ns " "Info: Found hold time violation between source pin or register \"Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" and destination pin or register \"Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" for clock \"Clk_SCL\" (Hold time is 1.2 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.400 ns + Largest " "Info: + Largest clock skew is 1.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 5.600 ns + Longest register " "Info: + Longest clock path from clock \"Clk_SCL\" to destination register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns Data_drive:inst\|Adc_SCL_Select 2 REG LC8_C1 1 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC8_C1; Fanout = 1; REG Node = 'Data_drive:inst\|Adc_SCL_Select'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.500 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 3.500 ns Data_drive:inst\|Adc_SCL 3 COMB LC1_C2 20 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 3.500 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "1.700 ns" { Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 5.600 ns Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 4 REG LC5_A3 15 " "Info: 4: + IC(2.100 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC5_A3; Fanout = 15; REG Node = 'Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "2.100 ns" { Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 46.43 % " "Info: Total cell delay = 2.600 ns ( 46.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 53.57 % " "Info: Total interconnect delay = 3.000 ns ( 53.57 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.2ns 0.7ns 2.1ns } { 0.0ns 1.3ns 0.3ns 1.0ns 0.0ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL source 4.200 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk_SCL\" to source register is 4.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.100 ns Data_drive:inst\|Adc_SCL 2 COMB LC1_C2 20 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.100 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.800 ns" { Clk_SCL Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 4.200 ns Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 3 REG LC5_A3 15 " "Info: 3: + IC(2.100 ns) + CELL(0.000 ns) = 4.200 ns; Loc. = LC5_A3; Fanout = 15; REG Node = 'Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "2.100 ns" { Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.100 ns 50.00 % " "Info: Total cell delay = 2.100 ns ( 50.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 50.00 % " "Info: Total interconnect delay = 2.100 ns ( 50.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "4.200 ns" { Clk_SCL Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.0ns 2.1ns } { 0.0ns 1.3ns 0.8ns 0.0ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.2ns 0.7ns 2.1ns } { 0.0ns 1.3ns 0.3ns 1.0ns 0.0ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "4.200 ns" { Clk_SCL Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.0ns 2.1ns } { 0.0ns 1.3ns 0.8ns 0.0ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns - " "Info: - Micro clock to output delay of source is 0.300 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.600 ns - Shortest register register " "Info: - Shortest register to register delay is 0.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 1 REG LC5_A3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A3; Fanout = 15; REG Node = 'Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.600 ns) 0.600 ns Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC5_A3 15 " "Info: 2: + IC(0.000 ns) + CELL(0.600 ns) = 0.600 ns; Loc. = LC5_A3; Fanout = 15; REG Node = 'Data_Read:inst1\|lpm_counter:cnt_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.600 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.600 ns 100.00 % " "Info: Total cell delay = 0.600 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.600 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.600 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns } { 0.0ns 0.6ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" { } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.2ns 0.7ns 2.1ns } { 0.0ns 1.3ns 0.3ns 1.0ns 0.0ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "4.200 ns" { Clk_SCL Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.200 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns 0.0ns 2.1ns } { 0.0ns 1.3ns 0.8ns 0.0ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.600 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.600 ns" { Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] Data_Read:inst1|lpm_counter:cnt_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } { 0.0ns 0.0ns } { 0.0ns 0.6ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "Data_drive:inst\|Adc_Conv En Clk_SCL 2.900 ns register " "Info: tsu for register \"Data_drive:inst\|Adc_Conv\" (data pin = \"En\", clock pin = \"Clk_SCL\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest pin register " "Info: + Longest pin to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns En 1 PIN PIN_40 2 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_40; Fanout = 2; PIN Node = 'En'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { En } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 160 -40 128 176 "En" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 2.300 ns Sample_Ctrl:inst2\|Sample_Ctrl_out~5 2 COMB LC2_C3 1 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 2.300 ns; Loc. = LC2_C3; Fanout = 1; COMB Node = 'Sample_Ctrl:inst2\|Sample_Ctrl_out~5'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "1.000 ns" { En Sample_Ctrl:inst2|Sample_Ctrl_out~5 } "NODE_NAME" } "" } } { "Sample_Ctrl.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Sample_Ctrl.v" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.800 ns) 3.200 ns Data_drive:inst\|Adc_Conv~169 3 COMB LC3_C3 1 " "Info: 3: + IC(0.100 ns) + CELL(0.800 ns) = 3.200 ns; Loc. = LC3_C3; Fanout = 1; COMB Node = 'Data_drive:inst\|Adc_Conv~169'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.900 ns" { Sample_Ctrl:inst2|Sample_Ctrl_out~5 Data_drive:inst|Adc_Conv~169 } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.700 ns) 4.000 ns Data_drive:inst\|Adc_Conv 4 REG LC7_C3 2 " "Info: 4: + IC(0.100 ns) + CELL(0.700 ns) = 4.000 ns; Loc. = LC7_C3; Fanout = 2; REG Node = 'Data_drive:inst\|Adc_Conv'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.800 ns" { Data_drive:inst|Adc_Conv~169 Data_drive:inst|Adc_Conv } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 95.00 % " "Info: Total cell delay = 3.800 ns ( 95.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 5.00 % " "Info: Total interconnect delay = 0.200 ns ( 5.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "4.000 ns" { En Sample_Ctrl:inst2|Sample_Ctrl_out~5 Data_drive:inst|Adc_Conv~169 Data_drive:inst|Adc_Conv } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { En En~out Sample_Ctrl:inst2|Sample_Ctrl_out~5 Data_drive:inst|Adc_Conv~169 Data_drive:inst|Adc_Conv } { 0.000ns 0.000ns 0.000ns 0.100ns 0.100ns } { 0.000ns 1.300ns 1.000ns 0.800ns 0.700ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" { } { { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 13 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock \"Clk_SCL\" to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns Data_drive:inst\|Adc_Conv 2 REG LC7_C3 2 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC7_C3; Fanout = 2; REG Node = 'Data_drive:inst\|Adc_Conv'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.200 ns" { Clk_SCL Data_drive:inst|Adc_Conv } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "1.500 ns" { Clk_SCL Data_drive:inst|Adc_Conv } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_Conv } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "4.000 ns" { En Sample_Ctrl:inst2|Sample_Ctrl_out~5 Data_drive:inst|Adc_Conv~169 Data_drive:inst|Adc_Conv } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.000 ns" { En En~out Sample_Ctrl:inst2|Sample_Ctrl_out~5 Data_drive:inst|Adc_Conv~169 Data_drive:inst|Adc_Conv } { 0.000ns 0.000ns 0.000ns 0.100ns 0.100ns } { 0.000ns 1.300ns 1.000ns 0.800ns 0.700ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "1.500 ns" { Clk_SCL Data_drive:inst|Adc_Conv } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.500 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_Conv } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.300ns 0.000ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk_SCL Current_Data\[4\] Data_Read:inst1\|Data\[8\] 11.000 ns register " "Info: tco from clock \"Clk_SCL\" to destination pin \"Current_Data\[4\]\" through register \"Data_Read:inst1\|Data\[8\]\" is 11.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL source 5.600 ns + Longest register " "Info: + Longest clock path from clock \"Clk_SCL\" to source register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns Data_drive:inst\|Adc_SCL_Select 2 REG LC8_C1 1 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC8_C1; Fanout = 1; REG Node = 'Data_drive:inst\|Adc_SCL_Select'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.500 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 58 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 3.500 ns Data_drive:inst\|Adc_SCL 3 COMB LC1_C2 20 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 3.500 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "1.700 ns" { Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 5.600 ns Data_Read:inst1\|Data\[8\] 4 REG LC3_A1 1 " "Info: 4: + IC(2.100 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC3_A1; Fanout = 1; REG Node = 'Data_Read:inst1\|Data\[8\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "2.100 ns" { Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 46.43 % " "Info: Total cell delay = 2.600 ns ( 46.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 53.57 % " "Info: Total interconnect delay = 3.000 ns ( 53.57 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } { 0.000ns 0.000ns 0.200ns 0.700ns 2.100ns } { 0.000ns 1.300ns 0.300ns 1.000ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns + Longest register pin " "Info: + Longest register to pin delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Data_Read:inst1\|Data\[8\] 1 REG LC3_A1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A1; Fanout = 1; REG Node = 'Data_Read:inst1\|Data\[8\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(3.800 ns) 5.100 ns Current_Data\[4\] 2 PIN PIN_7 0 " "Info: 2: + IC(1.300 ns) + CELL(3.800 ns) = 5.100 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'Current_Data\[4\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.100 ns" { Data_Read:inst1|Data[8] Current_Data[4] } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 216 808 1000 232 "Current_Data\[11..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 74.51 % " "Info: Total cell delay = 3.800 ns ( 74.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns 25.49 % " "Info: Total interconnect delay = 1.300 ns ( 25.49 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.100 ns" { Data_Read:inst1|Data[8] Current_Data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Data_Read:inst1|Data[8] Current_Data[4] } { 0.000ns 1.300ns } { 0.000ns 3.800ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.600 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL Data_Read:inst1|Data[8] } { 0.000ns 0.000ns 0.200ns 0.700ns 2.100ns } { 0.000ns 1.300ns 0.300ns 1.000ns 0.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "5.100 ns" { Data_Read:inst1|Data[8] Current_Data[4] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.100 ns" { Data_Read:inst1|Data[8] Current_Data[4] } { 0.000ns 1.300ns } { 0.000ns 3.800ns } } } } 0}
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