{ "Info" "ITDB_FULL_TPD_RESULT" "Clk_SCL Adc_SCL 6.000 ns Longest " "Info: Longest tpd from source pin \"Clk_SCL\" to destination pin \"Adc_SCL\" is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 2.100 ns Data_drive:inst\|Adc_SCL 2 COMB LC1_C2 20 " "Info: 2: + IC(0.000 ns) + CELL(0.800 ns) = 2.100 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.800 ns" { Clk_SCL Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(3.800 ns) 6.000 ns Adc_SCL 3 PIN PIN_50 0 " "Info: 3: + IC(0.100 ns) + CELL(3.800 ns) = 6.000 ns; Loc. = PIN_50; Fanout = 0; PIN Node = 'Adc_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "3.900 ns" { Data_drive:inst|Adc_SCL Adc_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 344 808 984 360 "Adc_SCL" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.900 ns 98.33 % " "Info: Total cell delay = 5.900 ns ( 98.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 1.67 % " "Info: Total interconnect delay = 0.100 ns ( 1.67 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "6.000 ns" { Clk_SCL Data_drive:inst|Adc_SCL Adc_SCL } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { Clk_SCL Clk_SCL~out Data_drive:inst|Adc_SCL Adc_SCL } { 0.000ns 0.000ns 0.000ns 0.100ns } { 0.000ns 1.300ns 0.800ns 3.800ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Data_Read:inst1\|Data\[15\] Adc_Data Clk_SCL 4.600 ns register " "Info: th for register \"Data_Read:inst1\|Data\[15\]\" (data pin = \"Adc_Data\", clock pin = \"Clk_SCL\") is 4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_SCL destination 5.600 ns + Longest register " "Info: + Longest clock path from clock \"Clk_SCL\" to destination register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns Clk_SCL 1 CLK PIN_39 9 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 9; CLK Node = 'Clk_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "" { Clk_SCL } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/main.bdf" { { 336 -40 128 352 "Clk_SCL" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 1.800 ns Data_drive:inst\|Adc_SCL_Select 2 REG LC8_C1 1 " "Info: 2: + IC(0.200 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC8_C1; Fanout = 1; REG Node = 'Data_drive:inst\|Adc_SCL_Select'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "0.500 ns" { Clk_SCL Data_drive:inst|Adc_SCL_Select } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.000 ns) 3.500 ns Data_drive:inst\|Adc_SCL 3 COMB LC1_C2 20 " "Info: 3: + IC(0.700 ns) + CELL(1.000 ns) = 3.500 ns; Loc. = LC1_C2; Fanout = 20; COMB Node = 'Data_drive:inst\|Adc_SCL'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "1.700 ns" { Data_drive:inst|Adc_SCL_Select Data_drive:inst|Adc_SCL } "NODE_NAME" } "" } } { "Data_drive.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_drive.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 5.600 ns Data_Read:inst1\|Data\[15\] 4 REG LC5_A1 1 " "Info: 4: + IC(2.100 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC5_A1; Fanout = 1; REG Node = 'Data_Read:inst1\|Data\[15\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/db/main.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/" "" "2.100 ns" { Data_drive:inst|Adc_SCL Data_Read:inst1|Data[15] } "NODE_NAME" } "" } } { "Data_Read.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current_adc_ctrl/main/Data_Read.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 46.43 % " "Info: Total cell delay = 2.600 ns ( 46.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 53.57 % " "Info: Total interconnect delay = 3.000 ns ( 53.57 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/DC_Motor/Current