/*----------------------------------------------------------------------------**    mx25L1605.v - 16M-BIT CMOS Serial eLiteFlash EEPROM**            COPYRIGHT 2001 BY Macronix International Corporation**-----------------------------------------------------------------------------*  Environment  : VCS*  Author       : C.M. Wu *  Creation Date: 2004/10/18*  VERSION      : V 0.02*  Note         : This model do not include test mode *  Description  : *                 module flash_16m -> behavior model for the 16M serial flash*-----------------------------------------------------------------------------*/`timescale 1ns / 10ps      // Define controller state      `define    STANDBY_STATE          0      `define    ACTION_STATE           1      `define    CMD_STATE              2      `define    BAD_CMD_STATE          3      `define    ERASE_TIME             1_000_000_000  //     1 s      `define    CHIP_ERASE_TIME           64_000_000  //    64 s      `define    PROG_TIME                  3_000_000  //     3 ms      // Time delay to write instruction       `define    PUW_TIME                  10_000_000  //    10 ms  `define    MX25L3205 //MX25L1605 MX25L3205 MX25L6405`ifdef MX25L1605        `define    FLASH_ADDR  21       `define    SECTOR_ADDR 7`else         `ifdef MX25L3205             `define    FLASH_ADDR  22             `define    SECTOR_ADDR 7       `else             `ifdef  MX25L6405                  `define    FLASH_ADDR  23                  `define    SECTOR_ADDR 7            `endif       `endif  `endif       `define FLASH_TYPE 0module flash_32m( SCLK, CS, SI, SO, PO0, PO1, PO2, PO3, PO4, PO5, PO6, WP);    //---------------------------------------------------------------------    // Declaration of ports (input,output, inout)    //---------------------------------------------------------------------    input  SCLK,    // Signal of Clock Input           CS,      // Chip select (Low active)           SI,      // Serial Data Input           WP;      // Write Protection:connect to GND    inout  SO,      // Serial Data Output // PO7/           PO6,     // Parallel data output                PO5,     // Parallel data output           PO4,     // Parallel data output           PO3,     // Parallel data output           PO2,     // Parallel data output           PO1,     // Parallel data output           PO0;     // Parallel data output               //---------------------------------------------------------------------    // Declaration of parameter (parameter)    //---------------------------------------------------------------------    parameter  FLASH_SIZE  = 1 << `FLASH_ADDR,  // 2M bytes               SECTOR_SIZE = 1 << 16,           // 64K bytes               FLASH_4kb_SIZE = 1 << 9,         // 4k bits               tAA     = 12,                    // Access Time [ns],tAA = tSKH + tCLQ               tC      = 20,                    // Clock Cycle Time,tC  = tSKH + tSKL                //tSKH   =  9,                   // Clock High Time               //tSKL   =  9,                   // Clock Low Time               tSHQZ   =  8,                    // CS High to SO Float Time [ns]               tCLQV   =  1,                    // Clock Low to Output Valid               tDP     =   3_000_000,           //   3 ms               tRES1   =  30_000_000,           //  30 ms               tRES2   =  30_000_000,           //  30 ms               tW_SRWD = 500_000_000,           // 500 ms               tW_BP   = 500_000_000,           // 500 ms               tW_WIP  =  30_000_000,           //  30 ms               tW_WEL  =  30_000_000;           //  30 ms        parameter  [7:0]  ID_MXIC   = 8'hc2;    `ifdef MX25L1605           parameter  [7:0]  ID_Device   = 8'h27;    // MX25L1605    `else            `ifdef MX25L3205                  parameter  [7:0]  ID_Device   = 8'h9d;    // MX25L3205           `else                 `ifdef MX25L6405                        parameter  [7:0]  ID_Device   = 8'h92;    // MX25L6405                  `endif                 `endif    `endif            parameter  [7:0]  WREN = 8'h06, //WriteEnable   = 8'h06,                      WRDI = 8'h04, //WriteDisable  = 8'h04,                      RDID = 8'h9F, //ReadID        = 8'h9f,                      RDSR = 8'h05, //ReadStatus    = 8'h05,                      WRSR = 8'h01, //WriteStatus   = 8'h01,                      READ = 8'h03, //ReadData      = 8'h03,                      FASTREAD = 8'h0b, //FastReadData  = 8'h0b,                      PARALLELMODE = 8'h55, //PallelMode    = 8'h55,                      SE1 = 8'h20, //SectorErase   = 8'h20,//8'hd8                      SE2 = 8'hd8, //SectorErase   = 8'h20,//8'hd8                      CE1 = 8'h60, //ChipErase     = 8'h60,//8'hc7                      CE2 = 8'hc7, //ChipErase     = 8'h60,//8'hc7                      PP = 8'h02, //PageProgram   = 8'h02,                      DP = 8'hb9, //DeepPowerDown = 8'hb9,                      EN4K = 8'ha5, //Enter4kbSector= 8'ha5,                      EX4K = 8'hb5, //Exit4kbSector = 8'hb5,                      RDP  = 8'hab, //ReleaseFromDeepPowerDwon = 8'hab,                      RES  = 8'hab, //ReadElectricID = 8'hab,                      REMS = 8'h90; //ReadElectricManufacturerDeviceID = 90;    //---------------------------------------------------------------------    // Declaration of internal-register (reg)    //---------------------------------------------------------------------    // memory array    reg  [7:0]       ROM_ARRAY[ 0:FLASH_SIZE-1 ];    reg  [7:0]       ROM_4Kb_ARRAY[ 0:FLASH_4kb_SIZE-1];    reg  [7:0]       status_reg;       // Status Register    reg  [256*8-1:0] si_reg;           // temp reg to store serial in    reg  [23:0]      address;          //     reg  [256*8-1:0] psi_reg;          // temp reg to store serial in    reg  [256*8-1:0] dummy_A;          // page size    reg  [12:0]      segment_addr;     // A[20:8] segment address    reg  [7:0]       offset_addr;      // A[7:0] means 256 bytes    reg  [`SECTOR_ADDR - 1:0]       sector;           // means 128 sectors    reg  [2:0]       state, rState;    reg  ENB_S0,ENB_P0,ENB_S1,ENB_P1;    reg  SO_reg;    reg  PO_reg6,PO_reg5,PO_reg4,PO_reg3,PO_reg2,PO_reg1,PO_reg0;    reg  latch_SO,latch_PO6,latch_PO5,latch_PO4,latch_PO3,latch_PO2,latch_PO1,latch_PO0;    reg  pp_p;    reg  pmode;        // parallel mode    reg  dpmode;       // deep power down mode    reg  enter4kbmode; // enter 4kb mode    reg  chip_erase_oe;    integer i,chip_erase_count;    wire wp_reg = WP;    //assign  {PO6,PO5,PO4,PO3,PO2,PO1,PO0} = WP ? 8'bz : {PO_reg6,PO_reg5,PO_reg4,PO_reg3,PO_reg2,PO_reg1,PO_reg0};    assign {SO,PO6,PO5,PO4,PO3,PO2,PO1,PO0} = pp_p ? 8'bz : {SO_reg,PO_reg6,PO_reg5,PO_reg4,PO_reg3,PO_reg2,PO_reg1,PO_reg0};    //assign {latch_SO,latch_PO6,latch_PO5,latch_PO4,latch_PO3,latch_PO2,latch_PO1,latch_PO0} = {SO,PO6,PO5,PO4,PO3,PO2,PO1,PO0};    always @(SO or PO6 or PO5 or PO4 or PO3 or PO2 or PO1 or PO0) begin          {latch_SO,latch_PO6,latch_PO5,latch_PO4,latch_PO3,latch_PO2,latch_PO1,latch_PO0} = {SO,PO6,PO5,PO4,PO3,PO2,PO1,PO0};          //latch_PO6 = PO6;    end    /*-------------------------------------------------------*/    /*  initial variable value                               */    /*-------------------------------------------------------*/        initial    begin         pp_p          = 1'b0;         enter4kbmode  = 1'b0;         dpmode        = 1'b0;         pmode         = 1'b0;         chip_erase_oe = 1'b0;         chip_erase_count = 0;         status_reg    = 8'b0000_0000;         {ENB_S0,ENB_P0,ENB_S1,ENB_P1} = {1'b1,1'b0,1'b0,1'b0};         i = 0;         while ( i < FLASH_4kb_SIZE ) begin             s_flash.ROM_4Kb_ARRAY[ i ] = 8'hFF;             i = i + 1;         end    end    /*-------------------------------------------------------*/    /*  latch signal SI into si_reg                          */    /*-------------------------------------------------------*/    always @( posedge SCLK ) begin        if ( $time > `PUW_TIME ) begin            if ( CS == 1'b0 ) begin                { si_reg[ 256*8-1:0 ] } = { si_reg[ 256*8-2:0 ], SI };            end        end     end    /*-------------------------------------------------------*/    /*  chip erase process                                   */    /*-------------------------------------------------------*/    always @( posedge chip_erase_oe ) begin        chip_erase_count = 0;        for ( chip_erase_count = 0;chip_erase_count<=`CHIP_ERASE_TIME;chip_erase_count=chip_erase_count+1)        begin        #1000;        end        //WIP : write in process bit        chip_erase_count = 0;        for( chip_erase_count = 0; chip_erase_count < FLASH_SIZE; chip_erase_count = chip_erase_count+1 )        begin            ROM_ARRAY[ chip_erase_count ] <= 8'hff;        end        chip_erase_count = 0;        //WIP : write in process bit        status_reg[0] <= 1'b0;//WIP        //WEL : write enable latch        status_reg[1] <= 1'b0;//WEL        chip_erase_oe = 1'b0;    end        /*-------------------------------------------------------*/    /*  Finite state machine to control Flash operation      */    /*-------------------------------------------------------*/    always @( posedge SCLK or posedge CS ) begin        if ( CS == 1'b1 ) begin    // Chip Disable            state <= #(tC-1) `STANDBY_STATE;           {SO_reg,PO_reg6,PO_reg5,PO_reg4,PO_reg3,PO_reg2,PO_reg1,PO_reg0} <= #tCLQV {1'bz,1'bz,1'bz,1'bz,1'bz,1'bz,1'bz,1'bz};        end        else begin    // Chip Enable            case ( state )                `STANDBY_STATE: begin                    {SO_reg,PO_reg6,PO_reg5,PO_reg4,PO_reg3,PO_reg2,PO_reg1,PO_reg0} <= #tCLQV {1'bz,1'bz,1'bz,1'bz,1'bz,1'bz,1'bz,1'bz};                    dummy_cycle( 6 );                    state <= #(tC-1) `CMD_STATE;                end                `CMD_STATE: begin                    #1;                    if ( si_reg[ 7:0 ] == WREN ) begin                        //$display( $stime, " Enter Write Enable Function ...");                        write_enable;                        //$display( $stime, " Leave Write Enable Function ...");                        state <= `STANDBY_STATE;                    end                     else if ( si_reg[ 7:0 ] == WRDI ) begin                        //$display( $stime, " Enter Write Disable Function ...");                        write_disable;                        //$display( $stime, " Leave Write Disable Function ...");                        state <= `STANDBY_STATE;                                            end                                        else if ( si_reg[ 7:0 ] == RDID ) begin                        //$display( $stime, " Enter Read ID Function ...");                        read_id;                        //$display( $stime, " Leave Read ID Function ...");                        state <= `STANDBY_STATE;                                            end                    else if ( si_reg[ 7:0 ] == RDSR ) begin                        //$display( $stime, " Enter Read Status Function ...");                        read_status ( status_reg );                        //$display( $stime, " Leave Read Status Function ...");                        state <= `STANDBY_STATE;                                            end                    else if ( si_reg[ 7:0 ] == WRSR ) begin                        //$display( $stime, " Enter Write Status Function ...");                        write_status;                        //$display( $stime, " Leave Write Status Function ...");                        state <= `STANDBY_STATE;                                            end                    else if ( si_reg[ 7:0 ] == READ ) begin                        //$display( $stime, " Enter Read Data Function ...");                        dummy_cycle( 24 );      // to get 24 bits address                        read_data;                        //$display( $stime, " Leave Read Data Function ...");                        state <= `STANDBY_STATE;