?? readme.html
字號:
<?xml version="1.0" ?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<title>USING THE IDE HARD DISK INTERFACE ON THE XST-3.0 BOARD</title>
<meta http-equiv="content-type" content="text/html; charset=utf-8" />
<link rev="made" href="mailto:" />
</head>
<body style="background-color: white">
<p><a name="__index__"></a></p>
<!-- INDEX BEGIN -->
<ul>
<li><a href="#using_the_ide_hard_disk_interface_on_the_xst3_0_board">USING THE IDE HARD DISK INTERFACE ON THE XST-3.0 BOARD</a></li>
<li><a href="#design_files">DESIGN FILES</a></li>
<li><a href="#using_the_design_example">USING THE DESIGN EXAMPLE</a></li>
<li><a href="#environment">ENVIRONMENT</a></li>
<li><a href="#source_files">SOURCE FILES</a></li>
<li><a href="#author">AUTHOR</a></li>
<li><a href="#copyright_and_license">COPYRIGHT AND LICENSE</a></li>
<li><a href="#history">HISTORY</a></li>
</ul>
<!-- INDEX END -->
<hr />
<p>
</p>
<hr />
<h1><a name="using_the_ide_hard_disk_interface_on_the_xst3_0_board">USING THE IDE HARD DISK INTERFACE ON THE XST-3.0 BOARD</a></h1>
<p>This is a simple design example that writes data to sectors
on an IDE hard disk and then reads it back to verify it.</p>
<p>
</p>
<hr />
<h1><a name="design_files">DESIGN FILES</a></h1>
<ul>
<li><strong><a name="item_common_2evhd"><em>common.vhd</em></a></strong>
<p>This file contains some definitions and functions used in the rest of the VHDL code.</p>
</li>
<li><strong><a name="item_atacntl_2evhd"><em>atacntl.vhd</em></a></strong>
<p>This is the VHDL file that describes an ATAPI interface to an IDE hard disk.
You can get a more detailed description of the interface at <a href="http://xess.com/appnotes/an-041404-atacntl.pdf">http://xess.com/appnotes/an-041404-atacntl.pdf</a> .</p>
</li>
<li><strong><a name="item_memtest_2evhd_2c_randgen_2evhd"><em>memtest.vhd</em>, <em>randgen.vhd</em></a></strong>
<p>These VHDL files describe a memory tester module that writes a stream of data from a random-number generator (RNG) to a storage
device and then reads the data back and compares it to the RNG output to verify it was stored correctly.</p>
</li>
<li><strong><a name="item_debounce_2evhd"><em>debounce.vhd</em></a></strong>
<p>This VHDL file describes a simple switch debouncer.</p>
</li>
<li><strong><a name="item_ide_2evhd"><em>ide.vhd</em></a></strong>
<p>This is the VHDL file that combines the IDE interface and memory tester module to create a design that tests
writes and reads of hard disk sectors.</p>
</li>
<li><strong><a name="item_ide_2eucf"><em>ide.ucf</em></a></strong>
<p>These are the constraints which assign the I/O signals of IDE interface to the
appropriate pins of the FPGA on the XSA-3S1000 + XST-3.0 combination.</p>
</li>
<li><strong><a name="item_ide_2ebit"><em>ide.bit</em></a></strong>
<p>This is a compiled bitstream for the design that can be downloaded into the XSA-3S1000 + XST-3.0 combination.</p>
</li>
<li><strong><a name="item_ide_2d200_2eucf"><em>ide-200.ucf</em></a></strong>
<p>This is an alternate set of pin assignments to be used if the design is recompiled for
an XSA-200 + XST-3.0 combination.</p>
</li>
<li><strong><a name="item_ide_2enpl"><em>ide.npl</em></a></strong>
<p>Open this project file with WebPACK if you need to recompile the design.</p>
</li>
</ul>
<p>
</p>
<hr />
<h1><a name="using_the_design_example">USING THE DESIGN EXAMPLE</a></h1>
<ul>
<li><strong><a name="item_step_1_3a">Step 1:</a></strong>
<p>Attach an ATX power supply to the XST-3.0 Board and an IDE hard disk.</p>
</li>
<li><strong><a name="item_step_2_3a">Step 2:</a></strong>
<p>Attach an IDE cable from header IDE1 on the XST-3.0 Board to the IDE hard disk.</p>
</li>
<li><strong><a name="item_step_3_3a">Step 3:</a></strong>
<p>Set jumper J9 on the XSA-3S1000 Board to XS.</p>
</li>
<li><strong><a name="item_step_4_3a">Step 4:</a></strong>
<p>Download the default parallel port interface into the XSA-3S1000 (<em>\XSTOOLS\XSA\3S1000\dwnldpar.svf</em>)
if it is not already present. (Running GXSTEST will do this automatically.)</p>
</li>
<li><strong><a name="item_step_5_3a">Step 5:</a></strong>
<p>Download the <em>ide.bit</em> file to the XSA Board.</p>
</li>
<li><strong><a name="item_step_6_3a">Step 6:</a></strong>
<p>After a 20-second delay, the application will write and read sectors on the hard disk and report
the success or failure of the operation by displaying an ``O'' or an ``E'' on LED2, respectively.
Press switch SW2 on the XSA Board to re-run the test.</p>
</li>
</ul>
<p>
</p>
<hr />
<h1><a name="environment">ENVIRONMENT</a></h1>
<p>This example design was developed using the following version of software:</p>
<pre>
Xilinx WebPACK : 6.3.03i</pre>
<p>
</p>
<hr />
<h1><a name="source_files">SOURCE FILES</a></h1>
<p>You can download the source files for this example design from the XESS website at
<a href="http://www.xess.com/projects/xst3_IDE.zip">http://www.xess.com/projects/xst3_IDE.zip</a> .</p>
<p>
</p>
<hr />
<h1><a name="author">AUTHOR</a></h1>
<p>Dave Vanden Bout, X Engineering Software Systems Corp.</p>
<p>Send bug reports to <a href="mailto:bugs@xess.com.">bugs@xess.com.</a></p>
<p>
</p>
<hr />
<h1><a name="copyright_and_license">COPYRIGHT AND LICENSE</a></h1>
<p>Copyright 2006 by X Engineering Software Systems Corporation.</p>
<p>This application can be freely distributed and modified
as long as you do not remove the attributions to the author or his employer.</p>
<p>
</p>
<hr />
<h1><a name="history">HISTORY</a></h1>
<p>05/30/2006 - Release 1.0.1:</p>
<ul>
<li>
<p>Added multisector R/W.</p>
</li>
<li>
<p>Added PIO Mode 2 timing parameters.</p>
</li>
<li>
<p>Added enhanced ATA status outputs.</p>
</li>
<li>
<p>Added outputs to inactivate the XSA Flash and IDE disk DMA acknowledge.</p>
</li>
<li>
<p>Added a switch input that re-runs the sector R/W test.</p>
</li>
</ul>
<p>01/30/2006 - Initial release.</p>
</body>
</html>
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -