module ram(DATA,ADDR,ENA,READ,WRITE);    inout[7:0] DATA;    input [9:0] ADDR;    input ENA;    input READ,WRITE;    reg[7:0] ram[10'h3ff:0];    assign DATA=(READ&&ENA)? ram[ADDR]:8'hzz;    always@(posedge WRITE)    begin        ram[ADDR]<=DATA;    endendmodule