library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity txt is
port (clk,wrn : in std_logic ;
	din : in std_logic_vector(7 downto 0) ;
	sdo  : out std_logic 
) ;
end txt ;

architecture v1 of txt is

signal counter1 : integer RANGE 0 TO 17;
signal counter2 : integer RANGE 0 TO 287;
signal clk1x_enable : std_logic ;
signal tsr : std_logic_vector (7 downto 0) ;
signal tbr : std_logic_vector (7 downto 0) ;
signal clkdiv :  unsigned (3 downto 0) ;
signal clk1x,clk16x :  std_logic ;
signal no_bits_sent :  unsigned (3 downto 0) ;
signal wrn1 :  std_logic ;
signal wrn2 :  std_logic ;

begin

--***************************************************************
process(clk,counter1,clk16x)
begin
	if rising_edge(clk) then
		if counter1=17 then
			counter1<=0;
			clk16x<=not clk16x;
		else
		 counter1<=counter1+1;
		end if;
	end if;
end process;	
--***************************************************************
process (clk,clk1x_enable)
begin
	if clk'event and clk = '1' then
		if clk1x_enable = '1' then
		IF counter2=287 then
		counter2<=0;
		clk1x<=not clk1x;
		else counter2<=counter2+1;
		end if;
		end if ;
	end if ;
end process ;
--***************************************************************


process (clk16x)
begin
if clk16x'event and clk16x = '1' then
wrn2 <= wrn1 ;
wrn1 <= wrn ;
end if ;
end process ;


process (clk16x)
begin
if clk16x'event and clk16x = '1' then
if wrn1 = '0' and wrn2 = '1' then 
clk1x_enable <= '1' ;
elsif std_logic_vector(no_bits_sent) = "1101" then
clk1x_enable <= '0' ;
end if ;
end if ;
end process ;

process (wrn)
begin
if wrn'event and wrn = '0' then
tbr <= din ;
end if ;
end process ;

process (clk1x,no_bits_sent,tbr)
begin
if clk1x'event and clk1x = '1' then
if std_logic_vector(no_bits_sent) = "0000" then
sdo<='1';
elsif std_logic_vector(no_bits_sent) = "0001" then
tsr <= tbr ;
elsif std_logic_vector(no_bits_sent) = "0010" then
sdo <= '0' ;
elsif std_logic_vector(no_bits_sent) >= "0011" and std_logic_vector(no_bits_sent) <= "1010" then
tsr <= '0'& tsr(7 downto 1)  ;
sdo <= tsr(0) ;
elsif std_logic_vector(no_bits_sent) = "1011" then
sdo<='1'; 
end if ;
end if ;
end process ;


process (clk1x,clk1x_enable)
begin
if clk1x_enable = '0' then
no_bits_sent <= "0000" ;
elsif clk1x'event and clk1x = '1' then
if clk1x_enable = '1' then
no_bits_sent <= no_bits_sent + "0001" ;
end if ;
end if ;
end process ;

end ;