?? acexep1k10tc100.fit.rpt
字號:
Fitter report for ACEXep1k10tc100
Mon Jan 07 20:11:19 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Equations
6. Input Pins
7. Output Pins
8. All Package Pins
9. Control Signals
10. Global & Other Fast Signals
11. Carry Chains
12. Non-Global High Fan-Out Signals
13. LAB
14. Local Routing Interconnect
15. LAB External Interconnect
16. Row Interconnect
17. LAB Column Interconnect
18. LAB Column Interconnect
19. Fitter Resource Usage Summary
20. Fitter Resource Utilization by Entity
21. Delay Chain Summary
22. Pin-Out File
23. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Mon Jan 07 20:11:19 2008 ;
; Quartus II Version ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name ; ACEXep1k10tc100 ;
; Top-level Entity Name ; led ;
; Family ; ACEX1K ;
; Device ; EP1K10TC100-3 ;
; Timing Models ; Final ;
; Total logic elements ; 66 / 576 ( 11 % ) ;
; Total pins ; 8 / 66 ( 12 % ) ;
; Total memory bits ; 0 / 12,288 ( 0 % ) ;
; Total PLLs ; 0 ;
+-----------------------+------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+--------------------+--------------------+
; Device ; EP1K10TC100-3 ; ;
; Use smart compilation ; Off ; Off ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; PCI I/O ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Logic Cell Insertion - Individual Logic Cells ; On ; On ;
; Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains ; On ; On ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Auto Global Clock ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
+------------------------------------------------------------+--------------------+--------------------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.fit.eqn.
+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+
; Name ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; I/O Standard ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+
; clk ; 39 ; -- ; -- ; 32 ; yes ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+-----------------+---------------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+-----------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; Name ; Pin # ; Row ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ;
+-----------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
; ledout[0] ; 10 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
; ledout[1] ; 16 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
; ledout[2] ; 19 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
; ledout[3] ; 20 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
; ledout[4] ; 27 ; -- ; 21 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
; ledout[5] ; 28 ; -- ; 20 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
; ledout[6] ; 29 ; -- ; 19 ; no ; no ; no ; no ; no ; no ; no ; no ; no ; LVTTL/LVCMOS ;
+-----------+-------+-----+------+--------------+--------------------------+---------------+----------------+-----------------+---------------+---------------+------------+---------------+--------------+
+-----------------------------------+
; All Package Pins ;
+-------+------------+--------------+
; Pin # ; Usage ; I/O Standard ;
+-------+------------+--------------+
; 1 ; ^CONF_DONE ; ;
; 2 ; ^nCEO ; ;
; 3 ; #TDO ; ;
; 4 ; VCC_IO ; ;
; 5 ; GND* ; ;
; 6 ; GND* ; ;
; 7 ; GND* ; ;
; 8 ; GND* ; ;
; 9 ; GND* ; ;
; 10 ; ledout[0] ; LVTTL/LVCMOS ;
; 11 ; GND_INT ; ;
; 12 ; VCC_INT ; ;
; 13 ; GND* ; ;
; 14 ; GND* ; ;
; 15 ; GND* ; ;
; 16 ; ledout[1] ; LVTTL/LVCMOS ;
; 17 ; VCC_IO ; ;
; 18 ; GND_INT ; ;
; 19 ; ledout[2] ; LVTTL/LVCMOS ;
; 20 ; ledout[3] ; LVTTL/LVCMOS ;
; 21 ; GND* ; ;
; 22 ; GND* ; ;
; 23 ; GND* ; ;
; 24 ; #TMS ; ;
; 25 ; ^nSTATUS ; ;
; 26 ; GND* ; ;
; 27 ; ledout[4] ; LVTTL/LVCMOS ;
; 28 ; ledout[5] ; LVTTL/LVCMOS ;
; 29 ; ledout[6] ; LVTTL/LVCMOS ;
; 30 ; GND* ; ;
; 31 ; GND* ; ;
; 32 ; GND* ; ;
; 33 ; GND* ; ;
; 34 ; GND* ; ;
; 35 ; VCC_INT ; ;
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