?? acexep1k10tc100.fit.rpt
字號:
+----------------------------------------------+
; Local Routing Interconnect ;
+-----------------------------+----------------+
; Local Routing Interconnects ; Number of LABs ;
+-----------------------------+----------------+
; 0 ; 68 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 2 ;
+-----------------------------+----------------+
+---------------------------------------------+
; LAB External Interconnect ;
+----------------------------+----------------+
; LAB External Interconnects ; Number of LABs ;
+----------------------------+----------------+
; 0 ; 55 ;
; 1 ; 9 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
+----------------------------+----------------+
+-----------------------------------------------------------------------------------------+
; Row Interconnect ;
+-------+--------------------+-----------------------------+------------------------------+
; Row ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ;
+-------+--------------------+-----------------------------+------------------------------+
; A ; 0 / 96 ( 0 % ) ; 0 / 48 ( 0 % ) ; 1 / 48 ( 2 % ) ;
; B ; 0 / 96 ( 0 % ) ; 0 / 48 ( 0 % ) ; 1 / 48 ( 2 % ) ;
; C ; 45 / 96 ( 46 % ) ; 0 / 48 ( 0 % ) ; 3 / 48 ( 6 % ) ;
; Total ; 45 / 288 ( 15 % ) ; 0 / 144 ( 0 % ) ; 5 / 144 ( 3 % ) ;
+-------+--------------------+-----------------------------+------------------------------+
+----------------------------+
; LAB Column Interconnect ;
+-------+--------------------+
; Col. ; Interconnect Used ;
+-------+--------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; 2 ; 0 / 24 ( 0 % ) ;
; 3 ; 0 / 24 ( 0 % ) ;
; 4 ; 0 / 24 ( 0 % ) ;
; 5 ; 0 / 24 ( 0 % ) ;
; 6 ; 0 / 24 ( 0 % ) ;
; 7 ; 0 / 24 ( 0 % ) ;
; 8 ; 0 / 24 ( 0 % ) ;
; 9 ; 0 / 24 ( 0 % ) ;
; 10 ; 0 / 24 ( 0 % ) ;
; 11 ; 0 / 24 ( 0 % ) ;
; 12 ; 0 / 24 ( 0 % ) ;
; 13 ; 0 / 24 ( 0 % ) ;
; 14 ; 0 / 24 ( 0 % ) ;
; 15 ; 0 / 24 ( 0 % ) ;
; 16 ; 0 / 24 ( 0 % ) ;
; 17 ; 0 / 24 ( 0 % ) ;
; 18 ; 0 / 24 ( 0 % ) ;
; 19 ; 1 / 24 ( 4 % ) ;
; 20 ; 3 / 24 ( 12 % ) ;
; 21 ; 1 / 24 ( 4 % ) ;
; 22 ; 0 / 24 ( 0 % ) ;
; 23 ; 0 / 24 ( 0 % ) ;
; 24 ; 0 / 24 ( 0 % ) ;
; Total ; 5 / 576 ( < 1 % ) ;
+-------+--------------------+
+---------------------------+
; LAB Column Interconnect ;
+-------+-------------------+
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 0 / 48 ( 0 % ) ;
; Total ; 0 / 48 ( 0 % ) ;
+-------+-------------------+
+-----------------------------------------------------+
; Fitter Resource Usage Summary ;
+--------------------------------+--------------------+
; Resource ; Usage ;
+--------------------------------+--------------------+
; Registers ; 32 / 576 ( 5 % ) ;
; Total LABs ; 0 / 72 ( 0 % ) ;
; Logic elements in carry chains ; 25 ;
; User inserted logic elements ; 0 ;
; I/O pins ; 8 / 66 ( 12 % ) ;
; -- Clock pins ; 1 ;
; -- Dedicated input pins ; 0 / 4 ( 0 % ) ;
; Global signals ; 1 ;
; EABs ; 0 / 3 ( 0 % ) ;
; Total memory bits ; 0 / 12,288 ( 0 % ) ;
; Total RAM block bits ; 0 / 12,288 ( 0 % ) ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 32 ;
; Total fan-out ; 175 ;
; Average fan-out ; 2.36 ;
+--------------------------------+--------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
; |led ; 66 (42) ; 32 ; 0 ; 8 ; 34 (10) ; 21 (21) ; 11 (11) ; 25 (1) ; |led ;
; |lpm_add_sub:add_rtl_0| ; 24 (0) ; 0 ; 0 ; 0 ; 24 (0) ; 0 (0) ; 0 (0) ; 24 (0) ; |led|lpm_add_sub:add_rtl_0 ;
; |addcore:adder| ; 24 (1) ; 0 ; 0 ; 0 ; 24 (1) ; 0 (0) ; 0 (0) ; 24 (1) ; |led|lpm_add_sub:add_rtl_0|addcore:adder ;
; |a_csnbuffer:result_node| ; 23 (23) ; 0 ; 0 ; 0 ; 23 (23) ; 0 (0) ; 0 (0) ; 23 (23) ; |led|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node ;
+------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------+
; Delay Chain Summary ;
+-----------+----------+-------------+
; Name ; Pin Type ; Pad to Core ;
+-----------+----------+-------------+
; clk ; Input ; OFF ;
; ledout[0] ; Output ; OFF ;
; ledout[1] ; Output ; OFF ;
; ledout[2] ; Output ; OFF ;
; ledout[3] ; Output ; OFF ;
; ledout[4] ; Output ; OFF ;
; ledout[5] ; Output ; OFF ;
; ledout[6] ; Output ; OFF ;
+-----------+----------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in D:/FPGAtest/ACEXep1k10tc100/ACEXep1k10tc100.pin.
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Mon Jan 07 20:11:16 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ACEXep1k10tc100 -c ACEXep1k10tc100
Info: Selected device EP1K10TC100-3 for design "ACEXep1k10tc100"
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Inserted 0 logic cells in first fitting attempt
Info: Started fitting attempt 1 on Mon Jan 07 2008 at 20:11:17
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Jan 07 20:11:19 2008
Info: Elapsed time: 00:00:03
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