+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Jan 07 20:11:22 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ACEXep1k10tc100 -c ACEXep1k10tc100
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 48.78 MHz between source register "counter[0]" and destination register "led1[4]" (period= 20.5 ns)
    Info: + Longest register to register delay is 19.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C2; Fanout = 3; REG Node = 'counter[0]'
        Info: 2: + IC(0.300 ns) + CELL(0.700 ns) = 1.000 ns; Loc. = LC5_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]'
        Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 1.200 ns; Loc. = LC6_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[1]'
        Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 1.400 ns; Loc. = LC7_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[2]'
        Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 1.600 ns; Loc. = LC8_C2; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[3]'
        Info: 6: + IC(0.500 ns) + CELL(0.200 ns) = 2.300 ns; Loc. = LC1_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[4]'
        Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 2.500 ns; Loc. = LC2_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[5]'
        Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 2.700 ns; Loc. = LC3_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[6]'
        Info: 9: + IC(0.000 ns) + CELL(0.200 ns) = 2.900 ns; Loc. = LC4_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[7]'
        Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 3.100 ns; Loc. = LC5_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[8]'
        Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 3.300 ns; Loc. = LC6_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[9]'
        Info: 12: + IC(0.000 ns) + CELL(0.200 ns) = 3.500 ns; Loc. = LC7_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[10]'
        Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 3.700 ns; Loc. = LC8_C4; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[11]'
        Info: 14: + IC(0.500 ns) + CELL(0.200 ns) = 4.400 ns; Loc. = LC1_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[12]'
        Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 4.600 ns; Loc. = LC2_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13]'
        Info: 16: + IC(0.000 ns) + CELL(0.200 ns) = 4.800 ns; Loc. = LC3_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[14]'
        Info: 17: + IC(0.000 ns) + CELL(0.200 ns) = 5.000 ns; Loc. = LC4_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[15]'
        Info: 18: + IC(0.000 ns) + CELL(0.200 ns) = 5.200 ns; Loc. = LC5_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[16]'
        Info: 19: + IC(0.000 ns) + CELL(0.200 ns) = 5.400 ns; Loc. = LC6_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[17]'
        Info: 20: + IC(0.000 ns) + CELL(0.200 ns) = 5.600 ns; Loc. = LC7_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[18]'
        Info: 21: + IC(0.000 ns) + CELL(0.200 ns) = 5.800 ns; Loc. = LC8_C6; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[19]'
        Info: 22: + IC(0.500 ns) + CELL(0.200 ns) = 6.500 ns; Loc. = LC1_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[20]'
        Info: 23: + IC(0.000 ns) + CELL(0.200 ns) = 6.700 ns; Loc. = LC2_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[21]'
        Info: 24: + IC(0.000 ns) + CELL(0.200 ns) = 6.900 ns; Loc. = LC3_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[22]'
        Info: 25: + IC(0.000 ns) + CELL(1.400 ns) = 8.300 ns; Loc. = LC4_C8; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[23]'
        Info: 26: + IC(0.300 ns) + CELL(1.600 ns) = 10.200 ns; Loc. = LC6_C8; Fanout = 1; COMB Node = 'reduce_nor~237'
        Info: 27: + IC(1.000 ns) + CELL(1.400 ns) = 12.600 ns; Loc. = LC7_C7; Fanout = 1; COMB Node = 'reduce_nor~241'
        Info: 28: + IC(0.300 ns) + CELL(1.400 ns) = 14.300 ns; Loc. = LC1_C7; Fanout = 9; COMB Node = 'reduce_nor~0'
        Info: 29: + IC(1.700 ns) + CELL(1.400 ns) = 17.400 ns; Loc. = LC5_C20; Fanout = 7; COMB Node = 'led1[0]~74'
        Info: 30: + IC(1.000 ns) + CELL(1.000 ns) = 19.400 ns; Loc. = LC2_C21; Fanout = 4; REG Node = 'led1[4]'
        Info: Total cell delay = 13.300 ns ( 68.56 % )
        Info: Total interconnect delay = 6.100 ns ( 31.44 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_C21; Fanout = 4; REG Node = 'led1[4]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "clk" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_C2; Fanout = 3; REG Node = 'counter[0]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tco from clock "clk" to destination pin "ledout[1]" through register "led1[1]" is 10.900 ns
    Info: + Longest clock path from clock "clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_39; Fanout = 32; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_C20; Fanout = 3; REG Node = 'led1[1]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_C20; Fanout = 3; REG Node = 'led1[1]'
        Info: 2: + IC(1.700 ns) + CELL(6.300 ns) = 8.000 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'ledout[1]'
        Info: Total cell delay = 6.300 ns ( 78.75 % )
        Info: Total interconnect delay = 1.700 ns ( 21.25 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jan 07 20:11:23 2008
    Info: Elapsed time: 00:00:01