#-- Synplicity, Inc.
#-- Version Synplify Pro 8.6.2
#-- Project file D:\Work\dds_20071031\dds.prj
#-- Written on Wed Oct 31 14:10:19 2007


#add_file options
add_file -verilog "dds.v"


#implementation: "rev_1"
impl -add rev_1 -type fpga

#device options
set_option -technology 500K
set_option -part A500K050

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 1.000
set_option -run_prop_extract 1
set_option -fanout_limit 12
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond Default
set_option -update_models_cp 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_format "edif"
project -result_file "rev_1/dds.edn"

#
#implementation attributes

set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "rev_1"