?? 21_test_13a.vhd
字號(hào):
--Page : 283
--Objective : Deadlock
--Filename : test_13a
--Author : Joseph Pick
entity Test_13a is
end Test_13a;
architecture Behave_1 of Test_13a is
signal A : NATURAL := 1;
signal B : NATURAL := 1;
begin
Inc_A:
process
begin
wait on B;
A <=A+1;
assert FALSE
report "Simulation time has processed : Inc_A"
severity NOTE;
end process Inc_A;
Inc_B:
process
begin
wait on A;
B <=B+1;
assert FALSE
report "Simulation time has processed : Inc_B"
severity NOTE;
end process Inc_B;
end Behave_1;
?? 快捷鍵說(shuō)明
復(fù)制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號(hào)
Ctrl + =
減小字號(hào)
Ctrl + -