library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity led is
port(q:out std_logic_vector(0 to 7);
	clk:in std_logic;
	rest:in std_logic);
end led;
architecture behave of led is
constant n:integer:=1000000;
signal clk1:std_logic;
signal clk2:std_logic;
signal temp:std_logic_vector(7 downto 0);
begin
p0:process(clk)
variable count:integer range 0 to n;
	begin
		if rising_edge(clk) then
			if count=n then
				count:=0;
				clk1<=not clk1;
			else 
				count:=count+1;
			end if;
		end if;			
end process p0;
 clk2<=clk1;

p1:process(clk2,rest)
begin
if(clk2'event and clk2='1')then
    if(rest='0')then 
        temp <="00000001"; 	
    else
        temp<=temp(6 downto 0)&temp(7);
        q<=temp;
    end if;
end if;
end process p1;	
end behave;