-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
-- Created on Tue Jul 24 20:04:04 2007

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

--  Entity Declaration

ENTITY addr_1 IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		cs : IN STD_LOGIC;
		cs_all : IN STD_LOGIC;
		addr : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		control_word : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END addr_1;


--  Architecture Body

ARCHITECTURE addr_architecture OF addr_1 IS
type states is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal current_state,next_state:states:=s0;


	
BEGIN


address:process(current_state)

begin
  case current_state is
  when s0=>control_word<="00000000";
       addr(3 downto 0)<="1000";
       next_state<=s1;
  when s1=>control_word<="10000100";
       addr(3 downto 0)<="0000";
       next_state<=s2;
  when s2=>control_word<="11000100";
       addr(3 downto 0)<="0001";
       next_state<=s3;
  when s3=>control_word<="10010100";
       addr(3 downto 0)<="0010";
       next_state<=s4;
  when s4=>control_word<="11010100";
       addr(3 downto 0)<="0011";
       next_state<=s5;
  when s5=>control_word<="10100100";
       addr(3 downto 0)<="0100";
       next_state<=s6;
  when s6=>control_word<="11100100";
       addr(3 downto 0)<="0101";
       next_state<=s7;
  when s7=>control_word<="10110100";
       addr(3 downto 0)<="0110";
       next_state<=s8;
  when s8=>control_word<="11110100";
       addr(3 downto 0)<="0111";
       next_state<=s0;
  when others=>control_word<="00000000";
       next_state<=s0;
  end case;
end process address;

process(cs_all,cs)
begin
  if cs_all='1' then current_state<=s0;
  elsif cs'event and cs='0' then
  current_state<=next_state;
  end if;
end process;


END addr_architecture;