library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity series_parallel is
Port (clk : in std_logic;   --BS
      
      series : in std_logic;
      fs : in std_logic;
      parallel : out std_logic_vector(23 downto 0)
      );                   
end series_parallel;

architecture behave of series_parallel is
signal rega,regb : std_logic_vector(23 downto 0);
signal n : integer range 0 to 23;

begin
process(clk)
begin
    if clk'event and clk='0' then
       rega(n)<=series;
    end if;
end process;

process(clk,fs)
begin
    if fs='1' then
       n<=0;
       
    elsif clk'event and clk='1' then
          n<=n+1;
    end if;
    if fs='1' and fs'event then
       parallel<=rega;
    end if;
end process;
end behave;