?? didq.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DIDQ is
Port (sys_clk : in std_logic;
reset : in std_logic;
digit_in : in std_logic_vector(11 downto 0);
fs : out std_logic;
digit_out : out std_logic);
end DIDQ;
architecture behave of DIDQ is
signal count : std_logic_vector (4 downto 0);
signal n : integer range 0 to 11;
begin
process(sys_clk,n)
variable digit : std_logic_vector(11 downto 0);
begin
digit:=digit_in;
if sys_clk'event and sys_clk='0' then
count<=count+1;
if n<=5 then
fs<='1';
n<=n+1;
elsif n=11 then
n<=0;
fs<='0';
else
fs<='0';
n<=n+1;
end if;
digit_out<=digit(n);
end if;
end process;
end behave;
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