library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fs_out3 is
Port (sys_clk : in std_logic;
      reset : in std_logic;
      digit_in : in std_logic_vector(11 downto 0);
      fs : out std_logic;
      digit_out : out std_logic);                   
end fs_out3;

architecture behave of fs_out3 is


signal count : std_logic_vector (4 downto 0);
signal n : integer range 0 to 11;

begin

process(sys_clk,n)
variable digit : std_logic_vector(11 downto 0);
begin
if reset='1' then
   digit:=digit_in;
   count<="00000";
   n<=0;
elsif sys_clk'event and sys_clk='0' then
      
       count<=count+1;
		if n=1 then
			fs<='1';
			n<=n+1;
		elsif n=11 then
            n<=0;
            fs<='0';
		else 
			fs<='0';
			n<=n+1;
		end if;

       digit_out<=digit(n);
end if;    

end process;

end behave;