library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
  port(
        clk:in std_logic;------掃描時鐘
        secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分別為秒個位/時位；分個位/
        daout:out std_logic_vector(3 downto 0);----------------輸出
        sel:out std_logic_vector(2 downto 0));-----位選信號
end SELTIME;
architecture fun of SELTIME is
   signal count:std_logic_vector(2 downto 0);----計數信號
begin
   sel<=count;
   process(clk)
          begin
              if(clk'event and clk='1') then
                 if(count>="111") then
                    count<="000";
                  else
                    count<=count+1;
                  end if;
               end if;
  case count is
  when"111"=>daout<= secm0;----秒個位
  when"110"=>daout<= secm1;----秒十位
  when"101"=>daout<= sec0;----分個位
  when"100"=>daout<= sec1;----分十位
  when"011"=>daout<=min0;   ----時個位
  when"010"=>daout<=min1;----時十位
  when"001"=>daout<=h0;
  when others =>daout<=h1;
  end case;
  end process;
end fun;