library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----輸入時鐘/高電平有效的使能信號
     h1,h0:out std_logic_vector(3 downto 0));----時高位/低位
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);----記數
begin
if clk'event and clk='1' then---上升沿觸發
if en='1' then---同時“使能”為1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";----高位/低位同時為0時
cnt0:="0000";
elsif cnt0<"1001" then----低位小于9時，低位記數累加
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;-----高位記數累加
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;