library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----時(shí)鐘/清零信號(hào)
     sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
     co:out std_logic);-------輸出/進(jìn)位信號(hào)
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---計(jì)數(shù)
begin
if clr='1' then----當(dāng)ckr為1時(shí)，高低位均為0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then----當(dāng)記數(shù)為58（實(shí)際是經(jīng)過(guò)59個(gè)記時(shí)脈沖）
co<='1';----進(jìn)位
cnt0:="1001";----低位為9
elsif cnt0<"1001" then----小于9時(shí)
cnt0:=cnt0+1;----計(jì)數(shù)
else
cnt0:="0000";

if cnt1<"0101" then----高位小于5時(shí)
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;