?? ccu.v
字號:
`timescale 1ns/10psmodule centercontroler(cmd1,cmd2,LE1,LE2, clk,reset, outCmd,cfloor1, cfloor2,status1,status2);output[2:0] cmd1;output[2:0] cmd2;output LE1;output LE2;input reset;input clk;input[3:0] outCmd;input[2:0] cfloor1;input[2:0] cfloor2;input[1:0] status1;input[1:0] status2;reg LE1;reg LE2;reg[3:0] temp;
reg[2:0] f1;
reg[2:0] f2;reg[2:0] cmd1;reg[2:0] cmd2; always@(posedge clk or negedge reset)//or outCmd) begin LE1='b0; LE2='b0; cmd1=0; cmd2=0;
f1=0;
f2=0; if(!reset) begin temp=0; end else if(temp!=outCmd && outCmd!='b0000 &&outCmd!='b1111) begin temp=outCmd; case ({status1,status2}) 'b0000: begin
if(cfloor1>outCmd[2:0])
f1=cfloor1-outCmd[2:0];
else
f1=outCmd[2:0]-cfloor1;
if(cfloor2>outCmd[2:0])
f2=cfloor2-outCmd[2:0];
else
f2=outCmd[2:0]-cfloor2;
if(f1<f2)
begin LE1='b1; cmd1=outCmd[2:0];
end
else
begin LE2='b1; cmd2=outCmd[2:0];
end end 'b0001: begin if(outCmd[3]) begin LE1='b1; cmd1=outCmd[2:0]; end else begin if(cfloor2<outCmd[2:0]) begin LE1='b1; cmd1=outCmd[2:0]; end else begin LE2='b1; cmd2=outCmd[2:0]; end end end 'b0011: begin if(outCmd[3]) begin if(cfloor2>outCmd[2:0]) begin LE1='b1; cmd1=outCmd[2:0]; end else begin LE2='b1; cmd2=outCmd[2:0]; end end else begin LE1='b1; cmd1=outCmd[2:0]; end end 'b0100: begin begin if(outCmd[3]) begin LE2='b1; cmd2=outCmd[2:0]; end else begin if(cfloor1<outCmd[2:0]) begin LE2='b1; cmd2=outCmd[2:0]; end else begin LE1='b1; cmd1=outCmd[2:0]; end end end end 'b0101: begin if(outCmd[3]) begin if(cfloor1>cfloor2) begin LE2='b1; cmd2=outCmd[2:0]; end else begin LE1='b1; cmd1=outCmd[2:0]; end end else begin case({outCmd[2:0]>cfloor1,outCmd[2:0]>cfloor2,cfloor1>cfloor2}) 'b001, 'b100, 'b111: begin LE2='b1; cmd2=outCmd[2:0]; end 'b000, 'b011, 'b110: begin LE1='b1; cmd1=outCmd[2:0]; end default: begin LE1='b0; LE2='b0; end endcase end end 'b0111: begin if(outCmd[3]) begin if(outCmd[2:0]>=cfloor2) begin LE2='b1; cmd2=outCmd[2:0]; end else begin LE1='b1; cmd1=outCmd[2:0]; end end else begin if(outCmd[2:0]<=cfloor1) begin LE1='b1; cmd1=outCmd[2:0]; end else begin LE2='b1; cmd2=outCmd[2:0]; end end end 'b1100: begin if(outCmd[3]) begin if(cfloor1>outCmd[2:0]) begin LE2='b1; cmd2=outCmd[2:0]; end else begin LE1='b1; cmd1=outCmd[2:0]; end end else begin LE2='b1; cmd2=outCmd[2:0]; end end 'b1101: begin if(outCmd[3]) begin if(outCmd[2:0]>=cfloor1) begin LE1='b1; cmd1=outCmd[2:0]; end else begin LE2='b1; cmd2=outCmd[2:0]; end end else begin if(outCmd[2:0]<=cfloor2) begin LE2='b1; cmd2=outCmd[2:0]; end else begin LE1='b1; cmd1=outCmd[2:0]; end end end 'b1111: begin if(~outCmd[3]) begin if(cfloor1>cfloor2) begin LE2='b1; cmd2=outCmd[2:0]; end else begin LE1='b1; cmd1=outCmd[2:0]; end end else begin case({outCmd[2:0]>=cfloor1,outCmd[2:0]>=cfloor2,cfloor1>=cfloor2}) 'b001, 'b100, 'b111: begin LE1='b1; cmd1=outCmd[2:0]; end 'b010, 'b000, 'b110: begin LE2='b1; cmd2=outCmd[2:0]; end default: begin LE1='b0; LE2='b0; end endcase end end default: begin LE1='b0; LE2='b0; end endcase end end endmodule ?? 快捷鍵說明
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