32位浮點(diǎn)乘法器vhdl源代碼

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is 
  port(x,y,z:in std_logic;s,c:out std_logic);
end full_adder;
architecture df of full_adder is
begin
s<=(x xor y)xor z;
c<=(x and y)or(x and z)or(y and z);
end df;
--????????N???????
library ieee;
use ieee.std_logic_1164.all;
entity generic_fa is--------------------------------加法器
	generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end generic_fa;

architecture conc of generic_fa is
  component full_adder
    port(x,y,z:in std_logic;s,c:out std_logic);
  end component;
  signal carry:std_logic_vector(n downto 0);
begin
  carry(0)<='0';
  cout<=carry(n);
  
  g1:for k in 0 to n-1 generate
   fa:full_adder port map (x=>a(k),y=>b(k),z=>carry(k),
                        s=>sum(k),c=>carry(k+1));
                    end generate;
end conc;    
--????????????
library ieee;
use ieee.std_logic_1164.all;
entity mul24 is------------------------------------------------24位乘法（尾數(shù)相乘）
    port(mplr:in std_logic_vector(23 downto 0);
         mpcd:in std_logic_vector(23 downto 0);
		 result_24:out std_logic_vector(23 downto 0));
end mul24;

architecture compact of mul24 is
  signal acarry:std_logic_vector(23 downto 0);
  type sum_type is array(23 downto 0) of
    std_logic_vector(23 downto 0);
  signal asum:sum_type;
  signal opd1,opd2:sum_type;
  signal res:std_logic_vector(47 downto 0);
  signal result:std_logic_vector(47 downto 0);
  
  function resize(a:in std_logic;size:in natural)--------------------------res="0000..0"或者"1111..1"
    return std_logic_vector is
    variable res:std_logic_vector(size-1 downto 0);
begin 
    res:=(others=>a);
    return(res);
end;

component generic_fa
	generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end component;
begin
    g2:for k in 1 to 23 generate
    g3:if k=1 generate
      asum(0)<=resize(mplr(0),24)and mpcd;
      result(0)<=asum(0)(0);
      acarry(0)<='0';
      end generate;
  
  opd2(k)<=acarry(k-1)& asum(k-1)(23 downto 1);
  opd1(k)<=resize(mplr(k),24)and mpcd;
  
  gfa:generic_fa 
    generic map(n=>24)
    port map(a=>opd1(k),b=>opd2(k),sum=>asum(k),
            cout=>acarry(k));
    result(k)<=asum(k)(0);
    end generate;
result(47 downto 24)<=acarry(23)& asum(23)(23 downto 1);
	g4:for k in 0 to 23 generate
		result_24(k)<=result(k+24);
		end generate;
end compact;


library ieee;
use ieee.std_logic_1164.all;
entity sub is 
  port(x,y,z:in std_logic;s,c:out std_logic);
end sub;
architecture asub of sub is
begin
s<=(x xor y)xor z;
c<=((not x)and y)or((not x)and z)or(y and z);
end asub;

library ieee;
use ieee.std_logic_1164.all;----------------------減法器
entity sub_n is
    generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end sub_n;

architecture asub_n of sub_n is
  component sub
    port(x,y,z:in std_logic;s,c:out std_logic);
  end component;
  signal carry:std_logic_vector(n downto 0);
begin
  carry(0)<='0';
  cout<=carry(n);
  
  g1:for k in 0 to n-1 generate
   fa:sub port map (x=>a(k),y=>b(k),z=>carry(k),
                        s=>sum(k),c=>carry(k+1));
                    end generate;
end asub_n; 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity float_mul is
port(mula,mulb:in std_logic_vector(31 downto 0);
	 --test:in std_logic_vector(1 downto 0):="00";
	 res_final:out std_logic_vector(31 downto 0));
end float_mul;
architecture afloat_mul of float_mul is
	signal sa,sb,sr,cout_e,cout_e1:std_logic;
	signal ea,eb,er1:std_logic_vector(7 downto 0);
	signal er:std_logic_vector(8 downto 0);
	signal fa,fb,fr,fr1:std_logic_vector(23 downto 0);
	shared variable er2:std_logic_vector(7 downto 0);
	
component generic_fa
	generic(n:natural);
    port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end component;
component sub_n
	generic(n:natural);
	port(a,b:in std_logic_vector(n-1 downto 0);
        sum:out std_logic_vector(n-1 downto 0);
        cout:out std_logic);
end component;
component mul24
	 port(mplr:in std_logic_vector(23 downto 0);
         mpcd:in std_logic_vector(23 downto 0);
		 result_24:out std_logic_vector(23 downto 0));
end component;
begin
	sa<=mula(31);
	sb<=mulb(31);
	ea<=mula(30 downto 23);
	eb<=mulb(30 downto 23);
	fa<='1'& mula(22 downto 0);
	fb<='1'& mulb(22 downto 0);
	sr<=sa xor sb;
	g5:generic_fa
	   generic map(n=>8)
		port map(a=>ea,b=>eb,sum=>er1,cout=>cout_e);
	g6:sub_n
		generic map(n=>9)
		port map(a=>cout_e&er1,b=>"001111111",sum=>er,cout=>cout_e1);
	g7:mul24
		port map(mplr=>fa,mpcd=>fb,result_24=>fr);

	
	process(er,fr,sr)
		begin
		er2:=er(7 downto 0);
	for k in 0 to 22 loop
		if(fr(23)='0')then
		fr1(k+1)<=fr(k);
		fr1(0)<='0';
		else
		fr1(k)<=fr(k);
		er2:=er2+1;
		end if;
		end loop;
		res_final(31)<=sr;
		res_final(30 downto 23)<=er2;
		res_final(22 downto 0)<=fr1(22 downto 0);
	end process;
end afloat_mul;