LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  use ieee.std_logic_arith.all;
--  USE ieee.std_logic_unsigned.ALL;
  USE work.pkg_types.ALL;
  USE work.pkg_components.ALL;

  ENTITY mem_sequence IS
	PORT(	clk	: IN bit1;
		reset	: IN bit1;
		sel_read: IN bit1;
		c_sel	: IN bit1;
		c_req	: OUT bit1;
		c_ack	: IN bit1;
		c_valid	: IN bit1;
                data_in : IN bit8;

		c_ad	: IN bit3;
                c       : OUT bit8;
                c_done  : OUT bit1);  
        END mem_sequence;

  ARCHITECTURE behavior OF mem_sequence IS
  SIGNAL  a1        :bit3_r;
  SIGNAL  addr      : std_logic_vector(2 downto 0);
  SIGNAL  sel_write      :bit1;
  BEGIN
   PROCESS
	
	PROCEDURE write_ram(sel_write:IN bit1;data:IN bit8) IS
	  BEGIN
		a1<=addr AFTER 2 ns;
      END write_ram;

     BEGIN
	  c_req <='0';
	  c_done <= '1';
	  addr <="000";
	  sel_write <= '0';

	  WAIT UNTIL(c_sel = '1' AND rising_edge(clk) AND reset = '1');

      c_done <='0';
	  c_req <='1';

	  WAIT UNTIL(c_ack='1' AND rising_edge(clk)) OR reset/='1';

	  c_req<='0';

	  write_loop:LOOP
		 IF c_valid/='1' AND addr/="111"  THEN
			 
			 WAIT UNTIL(c_valid='1' AND rising_edge(clk)) OR reset/='1';

			 IF reset/='1' THEN
				  EXIT write_loop;
             END IF;
          END IF;
		  --addr<=To_StdLogicVector(to_integer(addr+1),3);
		  addr<=addr+1;
		  write_ram(sel_write,data_in);
		  sel_write<='1';
		  IF addr="111" OR reset/='1' THEN
			  WAIT UNTIL rising_edge(clk);
			  EXIT write_loop;
           END IF;
		   WAIT UNTIL rising_edge(clk);
		   sel_write<='0';
		   END LOOP write_loop;
		   END PROCESS;

		   sequence_mem:mem_8x8
		   PORT MAP(c,data_in,c_ad,a1,sel_read,sel_write,clk);
    END behavior;