?? 3_mul.vhd
字號(hào):
entity mul is
port (
in1 : bit_vector;
in2 : bit_vector;
cntl : bit;
pout : out bit_vector
);
end mul;
architecture func of mul is
begin
process(cntl)
begin
if (cntl = '1') then
pout <= in1*in2;
end if;
end process;
end func;
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