--------------------------------------------------------------------------------
--
-- Traffic Light Controller (TLC) -- Simulation Vectors
--
-- Source:  Hardware C version  written by David Ku on June 8, 1988 at Stanford
--
-- VHDL Benchmark author Champaka Ramachandran
--                       University Of California, Irvine, CA 92717
--                       champaka@balboa.eng.uci.edu
--                 
-- Developed on Aug 11, 1992
--
-- Verification Information:
--
--                  Verified     By whom?           Date         Simulator
--                  --------   ------------        --------     ------------
--  Syntax            yes    Champaka Ramachandran  Aug 11, 92    ZYCAD
--  Functionality     yes    Champaka Ramachandran  Aug 11, 92    ZYCAD
--------------------------------------------------------------------------------

Entity E is
end;

architecture A of E is
       Component TLC
       port (
                       Cars : in  BIT;
                       TimeoutL : in  BIT;
                       TimeoutS : in  BIT;
                       StartTimer : out  BIT;
                       HiWay : out  Bit_Vector(2 Downto 0);
                       FarmL : out  Bit_Vector(2 Downto 0);
                       state : out  bit_vector(2 downto 0)
       );
       end component ;

                       signal Cars : BIT;
                       signal TimeoutL : BIT;
                       signal TimeoutS : BIT;
                       signal StartTimer : BIT;
                       signal HiWay : Bit_Vector(2 Downto 0);
                       signal FarmL : Bit_Vector(2 Downto 0);
                       signal state : bit_vector(2 downto 0);

for all : TLC use entity work.TLC(TLC) ;

begin

INST1 : TLC port map (
                       Cars,
                       TimeoutL,
                       TimeoutS,
                       StartTimer,
                       HiWay,
                       FarmL,
                       state
                    );

--process(StartTimer)
--begin
--	if ( StartTime = '1' ) then
--		TimeoutL <= '1' after 20 ns;
--	else
--		TimeoutL <= '0';
--	endif;
--end process;

--process(StartTimer)
--begin
--	if ( StartTime = '1' ) then
--		TimeoutS <= '1' after 3 ns;
--	else
--		TimeoutS <= '0';
--	endif;
--end process;

process


begin

-- ****************************************** 
-- *                                        * 
-- *           TEST VECTORS                 * 
-- *                                        * 
-- ****************************************** 
--
wait for 5 ns;
--
-- Pattern #0
Cars <= '1';
TimeoutL <= '1';
TimeoutS <= '0';
wait for 10 ns;


assert (StartTimer = '1')
report
"Assert 0 : < StartTimer /= 1 >"
severity error;

assert (HiWay = "010")
report
"Assert 0 : < HiWay /= 010 >"
severity warning;

assert (FarmL = "001")
report
"Assert 0 : < FarmL /= 001 >"
severity warning;

assert (state = "100")
report
"Assert 0 : < state /= 100 >"
severity warning;
--
-- Pattern #1
Cars <= '0';
TimeoutL <= '0';
TimeoutS <= '1';
wait for 10 ns;


assert (StartTimer = '1')
report
"Assert 1 : < StartTimer /= 1 >"
severity warning;

assert (HiWay = "001")
report
"Assert 1 : < HiWay /= 001 >"
severity warning;

assert (FarmL = "100")
report
"Assert 1 : < FarmL /= 100 >"
severity warning;

assert (state = "010")
report
"Assert 1 : < state /= 010 >"
severity warning;
--
-- Pattern #2
Cars <= '1';
TimeoutL <= '0';
TimeoutS <= '1';
wait for 10 ns;


assert (StartTimer = '0')
report
"Assert 2 : < StartTimer /= 0 >"
severity warning;

assert (HiWay = "001")
report
"Assert 2 : < HiWay /= 001 >"
severity warning;

assert (FarmL = "100")
report
"Assert 2 : < FarmL /= 100 >"
severity warning;

assert (state = "010")
report
"Assert 2 : < state /= 010 >"
severity warning;
--
-- Pattern #3
Cars <= '0';
TimeoutL <= '0';
TimeoutS <= '0';
wait for 10 ns;


assert (StartTimer = '1')
report
"Assert 3 : < StartTimer /= 1 >"
severity warning;

assert (HiWay = "001")
report
"Assert 3 : < HiWay /= 001 >"
severity warning;

assert (FarmL = "010")
report
"Assert 3 : < FarmL /= 010 >"
severity warning;

assert (state = "110")
report
"Assert 3 : < state /= 110 >"
severity warning;
--
-- Pattern #4
Cars <= '0';
TimeoutL <= '0';
TimeoutS <= '1';
wait for 10 ns;


assert (StartTimer = '1')
report
"Assert 4 : < StartTimer /= 1 >"
severity warning;

assert (HiWay = "100")
report
"Assert 4 : < HiWay /= 100 >"
severity warning;

assert (FarmL = "001")
report
"Assert 4 : < FarmL /= 001 >"
severity warning;

assert (state = "000")
report
"Assert 4 : < state /= 000 >"
severity warning;
--
-- Pattern #5
Cars <= '1';
TimeoutL <= '1';
TimeoutS <= '0';
wait for 10 ns;


assert (StartTimer = '1')
report
"Assert 5 : < StartTimer /= 1 >"
severity warning;

assert (HiWay = "010")
report
"Assert 5 : < HiWay /= 010 >"
severity warning;

assert (FarmL = "001")
report
"Assert 5 : < FarmL /= 001 >"
severity warning;

assert (state = "100")
report
"Assert 5 : < state /= 100 >"
severity warning;
--

--


assert false
report "---End of Simulation---"
severity error;

end process;

end A;