-- the VHDL description for 8-bit parity generator
-- Edit by yzf 1995

-- modfied by cdy Apr. 1998

package types is
   subtype short is integer range 0 to 255;
end types;
use work.types.all;

entity PARITY is
    port(IN0  	  : in bit;
		 IN1  	  : in bit;
		 IN2  	  : in bit;
		 IN3  	  : in bit;
		 IN4  	  : in bit;
		 IN5  	  : in bit;
		 IN6  	  : in bit;
		 IN7      : in bit;
		 EVEN_IN  : in bit;
		 ODD_IN	  : in bit;
		 IN_READY : in bit;
		 OUT_REQ  : in bit;
		 CLK 	  : in bit;
		 OUT_READY: out bit;
         ODD_OUT  : out bit;
         EVEN_OUT : out bit);
end PARITY;

-- The architecture body of the PARITY

architecture ALGORITHM of PARITY is
begin                                
	process
		variable cond:  boolean := true;
		variable count: short;
	begin	

    wait until CLK'event and CLK= '1' and IN_READY = '1';

	if EVEN_IN = ODD_IN then		-- parity error
	cond := false;
    end if;

 -- count the number of 1 on input
	count := 0;

	if IN0 = '1' then
		count := count + 1;
	end if;

	if IN1 = '1' then
		count := count + 1;
	end if;

	if IN2 = '1' then
		count := count + 1;
	end if;

	if IN3 = '1' then
		count := count + 1;
	end if;

	if IN4 = '1' then
		count := count + 1;
	end if;

	if IN5 = '1' then
		count := count + 1;
	end if;

	if IN6 = '1' then
		count := count + 1;
	end if;

	if IN7 = '1' then
		count := count + 1;
	end if;

-- judge count is even or odd

	L1: while count > 1 loop
		count := count - 2;
	end loop L1;

-- judge even_in odd_in

    if count = 1 and odd_in = '0' then
         cond := false;
    end if;
    if count = 0 and even_in = '0' then
         cond := false;
    end if;
   
-- output

	if count = 1 then
		EVEN_OUT <= '0';
        ODD_OUT  <= '1';
	else
		EVEN_OUT <= '1';
        ODD_OUT   <= '0';
	end if;		

    wait until CLK'event and CLK= '1' and OUT_REQ = '1';
	OUT_READY <= '1';
    wait until CLK'event and CLK= '1' and OUT_REQ = '0';
	OUT_READY <= '0';
   

    assert cond 
    report "odd_in even_in error"
    severity warning;

	end process;
end ALGORITHM;