----------------------------------------------------------------------------
-- lvds transmitter megafunction 
----------------------------------------------------------------------------
    
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity altlvds_tx is
    generic
      ( number_of_channels     : natural;
        deserialization_factor : natural;
        inclock_boost 	       : natural := 0;
        outclock_divide_by     : positive := 1;
        registered_input       : string := "ON";
        multi_clock            : string := "OFF";
        inclock_period         : natural;
        clock_setting          : string := "UNUSED";
        center_align_msb       : string := "UNUSED";
        intended_device_family : string := "APEX20KE";

	output_data_rate	: natural := 0;
	common_rx_tx_pll	: string := "ON";
	inclock_data_alignment  : string := "EDGE_ALIGEND";
	outclock_alignment : string := "EDGE_ALIGNED"
	);
    port
      ( tx_in           : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
        tx_inclock      : in std_logic;
        sync_inclock    : in std_logic := '0';
        tx_pll_enable   : in std_logic := '1';
        tx_out          : out std_logic_vector(number_of_channels-1 downto 0);
        tx_outclock     : out std_logic;
        tx_coreclock    : out std_logic;
        tx_locked       : out std_logic );

function clock_boost_calc (constant i_input_data_rate, i_inclock_period, i_deserialization_factor, i_inclock_boost : in natural) return natural is
variable i_input_clock_boost: natural;
begin
if (i_input_data_rate /= 0 and i_inclock_period /= 0) then
			i_input_clock_boost := (i_input_data_rate * 100) / i_inclock_period;
		else
			if inclock_boost =0 then
				i_input_clock_boost := i_deserialization_factor;
			else
				i_input_clock_boost := i_inclock_boost;
			end if;
		end if;
return i_input_clock_boost;

end clock_boost_calc; 

function get_phase_delay (constant i_phase_delay : in string) return string is
variable my_phase : string (1 to 11);
begin
-- returns the delay in radians 
if i_phase_delay = "EDGE_ALIGNED" then
	my_phase := "0.000000000";
elsif i_phase_delay = "CENTER_ALIGNED" then
	my_phase := "1.570796326";
elsif i_phase_delay = "45_DEGREES" then
	my_phase := "0.785398163";
elsif i_phase_delay = "135_DEGREES" then
	my_phase := "2.356194490";
elsif i_phase_delay = "180_DEGREES" then
	my_phase := "3.141592653";
elsif i_phase_delay = "225_DEGREES" then
	my_phase := "3.926990816";
elsif i_phase_delay = "270_DEGREES" then
	my_phase := "4.712388980";
elsif i_phase_delay = "315_DEGREES" then
	my_phase := "5.497787143";
end if;

return my_phase;

end get_phase_delay;

	function int_to_str( value : integer ) return string is
	variable ivalue,index : integer;
	variable digit : integer;
    variable line_no: string(8 downto 1) := "        ";  
	begin
		ivalue := value;
		index := 1;
		while (ivalue > 0) loop
			digit := ivalue MOD 10;
			ivalue := ivalue/10;
			case digit is
				when 0 =>
					line_no(index) := '0';
				when 1 =>
					line_no(index) := '1';
				when 2 =>
					line_no(index) := '2';
				when 3 =>
					line_no(index) := '3';
				when 4 =>
					line_no(index) := '4';
				when 5 =>
					line_no(index) := '5';
				when 6 =>
					line_no(index) := '6';
				when 7 =>
					line_no(index) := '7';
				when 8 =>
					line_no(index) := '8';
				when 9 =>
					line_no(index) := '9';
				when others =>
					ASSERT FALSE
					REPORT "Illegal number!"
					SEVERITY ERROR;
			end case;
			index := index + 1;
		end loop;
		return line_no;
	end;



end altlvds_tx;

architecture behavior of altlvds_tx is

signal tx_hold_rgd : std_logic_vector(deserialization_factor*number_of_channels -1 downto 0) := (others => '0');
signal tx_rgd : std_logic_vector(deserialization_factor*number_of_channels -1 downto 0) := (others => '0');
signal tx_in_int, data_int : std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
signal tx_clock0_int: std_logic;
signal tx_clock1_int: std_logic;
signal tx_pll_clk0: std_logic; 
signal tx_pll_clk1: std_logic; 
signal tx_pll_clk2: std_logic; 
signal tx_pll_clk2_deser: std_logic; 
signal tx_pll_clk2_boost: std_logic; 
signal apex20ke_locked_int: std_logic;
signal apex20ke_pll_clk0: std_logic; 
signal apex20ke_pll_clk1: std_logic; 
signal mercury_locked_int_boost: std_logic;
signal mercury_pll_clk0_boost: std_logic; 
signal mercury_pll_clk1_boost: std_logic; 
signal mercury_locked_int_deser: std_logic;
signal mercury_pll_clk0_deser: std_logic; 
signal mercury_pll_clk1_deser: std_logic; 
signal mercury_locked_int: std_logic;
signal mercury_pll_clk0: std_logic; 
signal mercury_pll_clk1: std_logic; 
signal tx_mercury_core_clock : std_logic;
signal tx_rgd_clk: std_logic; 
signal tx_locked_int: std_logic; 
signal apex20ke_en: std_logic;
signal mercury_en: std_logic;
signal mercury_boost_en: std_logic;
signal phase_inclock : integer;
signal phase_outclock : integer;
signal int_clock_boost : integer;
signal temp_zero : std_logic := '0';
signal temp_high : std_logic_vector (1 to 5)  := (others => '1');
signal temp_clk : std_logic_vector  (1 to 3):= (others => '0');


component altclklock
    generic
      ( inclock_period       : natural := 10000;
        clock0_boost         : natural := 1;
        clock1_boost         : natural := 1;
        clock1_divide        : natural := 1;
        clock2_boost         : natural := 1;
        clock2_divide        : natural := 1;
        valid_lock_cycles    : natural := 5;
        intended_device_family  : string := "APEX20KE";
			clock0_time_delay : string := "0";
			clock1_time_delay : string := "0" );
    port
      ( inclock   : in std_logic;
        inclocken : in std_logic;
        clock0    : out std_logic;
        clock1    : out std_logic;
        clock2    : out std_logic;
        locked    : out std_logic );
end component;

component altpll 
	generic (	
                inclk0_input_frequency  : positive ;
                clk1_multiply_by     : positive := 1;
					    clk0_multiply_by     : positive := 1;
						  clk2_multiply_by     : positive := 1;
							clk1_divide_by     	: positive := 1;
						  clk2_divide_by     	: positive := 1;
		           clk0_phase_shift     : string := "0";
						  clk1_phase_shift     : string := "0";
		           device_family : string := "Stratix"
	);
	port (