I 000035 56 942 1071731857737 dffe(_unit dffe	(_specify		(_specparam TRSU integer 0)		(_specparam TREN integer 0)		(_specparam TREG integer 0)		(_specparam TRCL integer 0)		(_specparam TRH integer 0)		(_specparam TRPR integer 0)		(_tchk setup 0 132			(_port D)			(_port CLK (posedge) (_code  1 legal))			(_register (viol_notifier))		)		(_tchk hold 0 133			(_port CLK (posedge) (_code  2 legal))			(_port D)			(_register (viol_notifier))		)		(_tchk setup 0 134			(_port ENA)			(_port CLK (posedge) (_code  3 legal))			(_register (viol_notifier))		)		(_tchk hold 0 135			(_port CLK (posedge) (_code  4 legal))			(_port ENA)			(_register (viol_notifier))		)		(_modpath parallel positive 0 137			(_port CLRN in negedge)			(_port Q out negedge)		)		(_modpath parallel positive 0 138			(_port PRN in negedge)			(_port Q out negedge)		)		(_modpath parallel positive 0 139			(_port CLK in posedge)			(_port Q out posedge)			(_datain D)		)	))I 000036 56 558 1071731857743 latch(_unit latch	(_specify		(_tchk setup 0 155			(_port D)			(_port ENA (posedge))		)		(_tchk hold 0 156			(_port ENA (negedge))			(_port D)		)		(_modpath parallel unknown 0 158			(_port D in )			(_port Q out )		)		(_modpath parallel positive 0 159			(_port ENA in posedge)			(_port Q out posedge)			(_datain q_out)		)		(_modpath parallel positive 0 160			(_port PRE in negedge)			(_port Q out negedge)			(_datain q_out)		)		(_modpath parallel positive 0 161			(_port CLR in negedge)			(_port Q out negedge)			(_datain q_out)		)	))I 000036 56 254 1071731857748 mux21(_unit mux21	(_specify		(_modpath parallel unknown 0 210			(_port A in )			(_port MO out )		)		(_modpath parallel unknown 0 211			(_port B in )			(_port MO out )		)		(_modpath parallel unknown 0 212			(_port S in )			(_port MO out )		)	))I 000035 56 104 1071731857753 and1(_unit and1	(_specify		(_modpath parallel unknown 0 227			(_port IN1 in )			(_port Y out )		)	))I 000036 56 105 1071731857758 and16(_unit and16	(_specify		(_modpath parallel unknown 0 240			(_port IN1 in )			(_port Y out )		)	))I 000052 56 2678 1071731857779 stratix_asynch_lcell(_unit stratix_asynch_lcell	(_specify		(_modpath parallel unknown 0 352			(_port dataa in )			(_port combout out )		)		(_modpath parallel unknown 0 353			(_port datab in )			(_port combout out )		)		(_modpath parallel unknown 0 354			(_port datac in )			(_port combout out )		)		(_modpath parallel unknown 0 355			(_port datad in )			(_port combout out )		)		(_modpath parallel unknown 0 356			(_port cin in )			(_port combout out )		)		(_modpath parallel unknown 0 357			(_port cin0 in )			(_port combout out )		)		(_modpath parallel unknown 0 358			(_port cin1 in )			(_port combout out )		)		(_modpath parallel unknown 0 359			(_port inverta in )			(_port combout out )		)		(_modpath parallel unknown 0 360			(_port qfbkin in )			(_port combout out )		)		(_modpath parallel unknown 0 362			(_port dataa in )			(_port cout out )		)		(_modpath parallel unknown 0 363			(_port datab in )			(_port cout out )		)		(_modpath parallel unknown 0 364			(_port cin in )			(_port cout out )		)		(_modpath parallel unknown 0 365			(_port cin0 in )			(_port cout out )		)		(_modpath parallel unknown 0 366			(_port cin1 in )			(_port cout out )		)		(_modpath parallel unknown 0 367			(_port inverta in )			(_port cout out )		)		(_modpath parallel unknown 0 369			(_port dataa in )			(_port cout0 out )		)		(_modpath parallel unknown 0 370			(_port datab in )			(_port cout0 out )		)		(_modpath parallel unknown 0 371			(_port cin0 in )			(_port cout0 out )		)		(_modpath parallel unknown 0 372			(_port inverta in )			(_port cout0 out )		)		(_modpath parallel unknown 0 374			(_port dataa in )			(_port cout1 out )		)		(_modpath parallel unknown 0 375			(_port datab in )			(_port cout1 out )		)		(_modpath parallel unknown 0 376			(_port cin1 in )			(_port cout1 out )		)		(_modpath parallel unknown 0 377			(_port inverta in )			(_port cout1 out )		)		(_modpath parallel unknown 0 379			(_port dataa in )			(_port regin out )		)		(_modpath parallel unknown 0 380			(_port datab in )			(_port regin out )		)		(_modpath parallel unknown 0 381			(_port datac in )			(_port regin out )		)		(_modpath parallel unknown 0 382			(_port datad in )			(_port regin out )		)		(_modpath parallel unknown 0 383			(_port cin in )			(_port regin out )		)		(_modpath parallel unknown 0 384			(_port cin0 in )			(_port regin out )		)		(_modpath parallel unknown 0 385			(_port cin1 in )			(_port regin out )		)		(_modpath parallel unknown 0 386			(_port inverta in )			(_port regin out )		)		(_modpath parallel unknown 0 387			(_port qfbkin in )			(_port regin out )		)	))I 000054 56 1583 1071731857784 stratix_lcell_register(_unit stratix_lcell_register	(_specify		(_tchk setuphold 0 708			(_port clk (posedge) (_code  5 reset))			(_port regcascin)			(_register (regcascin_viol))		)		(_tchk setuphold 0 709			(_port clk (posedge) (_code  6 reset))			(_port datain)			(_register (datain_viol))		)		(_tchk setuphold 0 710			(_port clk (posedge) (_code  7 reset))			(_port datac)			(_register (datac_viol))		)		(_tchk setuphold 0 711			(_port clk (posedge) (_code  8 reset))			(_port sclr)			(_register (sclr_viol))		)		(_tchk setuphold 0 712			(_port clk (posedge) (_code  9 reset))			(_port sload)			(_register (sload_viol))		)		(_tchk setuphold 0 713			(_port clk (posedge) (_code  10 reset))			(_port ena)			(_register (ena_viol))		)		(_modpath parallel positive 0 715			(_port clk in posedge)			(_port regout out posedge)			(_datain iregout)		)		(_modpath parallel positive 0 716			(_port aclr in posedge)			(_port regout out posedge)		)		(_modpath parallel positive 0 717			(_port aload in posedge)			(_port regout out posedge)			(_datain iregout)		)		(_modpath parallel unknown 0 718			(_port datac in )			(_port regout out )		)		(_modpath parallel positive 0 719			(_port clk in posedge)			(_port qfbkout out posedge)			(_datain iregout)		)		(_modpath parallel positive 0 720			(_port aclr in posedge)			(_port qfbkout out posedge)		)		(_modpath parallel positive 0 721			(_port aload in posedge)			(_port qfbkout out posedge)			(_datain iregout)		)		(_modpath parallel unknown 0 722			(_port datac in )			(_port qfbkout out )		)	))I 000048 56 593 1071731857793 stratix_asynch_io(_unit stratix_asynch_io	(_specify		(_modpath parallel unknown 0 890			(_port padio in )			(_port combout out )		)		(_modpath parallel unknown 0 891			(_port datain in )			(_port padio out )		)		(_modpath parallel positive 0 892			(_port oe in posedge)			(_port padio out posedge)			(_datain padio_tmp)		)		(_modpath parallel positive 0 893			(_port oe in negedge)			(_port padio out negedge)		)		(_modpath parallel unknown 0 894			(_port ddioregin in )			(_port ddioregout out )		)		(_modpath parallel unknown 0 895			(_port regin in )			(_port regout out )		)	))I 000050 56 785 1071731857798 stratix_io_register(_unit stratix_io_register	(_specify		(_tchk setuphold 0 1060			(_port clk (posedge) (_code  7 reset))			(_port datain)			(_register (datain_viol))		)		(_tchk setuphold 0 1061			(_port clk (posedge) (_code  8 reset))			(_port sreset)			(_register (sreset_viol))		)		(_tchk setuphold 0 1062			(_port clk (posedge) (_code  9 reset))			(_port ena)			(_register (ena_viol))		)		(_modpath parallel positive 0 1064			(_port clk in posedge)			(_port regout out posedge)			(_datain iregout)		)		(_modpath parallel positive 0 1067			(_code  10 is_areset_clear_EQ_1)			(_port areset in posedge)			(_port regout out posedge)		)		(_modpath parallel positive 0 1069			(_code  11 is_areset_preset_EQ_1)			(_port areset in posedge)			(_port regout out posedge)		)	))I 000052 56 1009 1071731857811 stratix_mac_register(_unit stratix_mac_register	(_specify		(_specparam TCLR_MIN_PW integer 0)		(_specparam TCLKL integer 0)		(_specparam TPRE_MIN_PW integer 0)		(_specparam TSU integer 0)		(_specparam TCLKH integer 0)		(_specparam TCLR integer 0)		(_specparam TCO integer 0)		(_specparam TCE_MIN_PW integer 0)		(_specparam TCLK_MIN_PW integer 0)		(_specparam TPRE integer 0)		(_specparam TH integer 0)		(_tchk setup 0 2392			(_port data)			(_port clk (posedge))			(_register (viol_notifier))		)		(_tchk hold 0 2393			(_port clk (posedge))			(_port data)			(_register (viol_notifier))		)		(_tchk setup 0 2394			(_port ena)			(_port clk (posedge))			(_register (viol_notifier))		)		(_tchk hold 0 2395			(_port clk (posedge))			(_port ena)			(_register (viol_notifier))		)		(_modpath parallel positive 0 2397			(_port aclr in posedge)			(_port dataout out posedge)		)		(_modpath parallel positive 0 2398			(_port clk in posedge)			(_port dataout out posedge)			(_datain dataout_tmp)		)	))I 000056 56 545 1071731857816 stratix_mac_mult_internal(_unit stratix_mac_mult_internal	(_specify		(_modpath full unknown 0 1463			(_port dataa in )			(_port dataout out )		)		(_modpath full unknown 0 1464			(_port datab in )			(_port dataout out )		)		(_modpath parallel unknown 0 1465			(_port dataa in )			(_port scanouta out )		)		(_modpath parallel unknown 0 1466			(_port datab in )			(_port scanoutb out )		)		(_modpath full unknown 0 1467			(_port signa in )			(_port dataout out )		)		(_modpath full unknown 0 1468			(_port signb in )			(_port dataout out )		)	))I 000056 56 1303 1071731857825 stratix_mac_out_internal(_unit stratix_mac_out_internal	(_specify		(_modpath full unknown 0 1928			(_port dataa in )			(_port dataout out )		)		(_modpath full unknown 0 1929			(_port datab in )			(_port dataout out )		)		(_modpath full unknown 0 1930			(_port datac in )			(_port dataout out )		)		(_modpath full unknown 0 1931			(_port datad in )			(_port dataout out )		)		(_modpath full unknown 0 1932			(_port signx in )			(_port dataout out )		)		(_modpath full unknown 0 1933			(_port signy in )			(_port dataout out )		)		(_modpath full unknown 0 1934			(_port addnsub0 in )			(_port dataout out )		)		(_modpath full unknown 0 1935			(_port addnsub1 in )			(_port dataout out )		)		(_modpath full unknown 0 1936			(_port zeroacc in )			(_port dataout out )		)		(_modpath full unknown 0 1937			(_port dataa in )			(_port accoverflow out )		)		(_modpath full unknown 0 1938			(_port signx in )			(_port accoverflow out )		)		(_modpath full unknown 0 1939			(_port signy in )			(_port accoverflow out )		)		(_modpath full unknown 0 1940			(_port addnsub0 in )			(_port accoverflow out )		)		(_modpath full unknown 0 1941			(_port addnsub1 in )			(_port accoverflow out )		)		(_modpath full unknown 0 1942			(_port zeroacc in )			(_port accoverflow out )		)	))I 000052 56 1322 1071731857830 stratix_ram_register(_unit stratix_ram_register	(_specify		(_specparam TCLR_MIN_PW integer 0)		(_specparam TCLKL integer 0)		(_specparam TPRE_MIN_PW integer 0)		(_specparam TSU integer 0)		(_specparam TCLKH integer 0)		(_specparam TCLR integer 0)