## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jan 26 14:37:29 涓?鍥芥爣鍑嗘椂闂? 2008
##
vlib work
vlog  "serial.v"
vlog  "dcmclk.v"
vlog  "ad9957_single.v"
vlog  "modulator.v"
vlog  "modulator_sim.v"
vlog  "D:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver -lib work modulator_sim_v glbl
do {modulator_sim_v.udo}
view wave
add wave *
add wave /glbl/GSR
view structure
view signals
run 1000ns