Release 8.1.03i par I.27Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.IBM-FD6C2779170::  Wed Jan 30 20:21:44 2008par -w -intstyle ise -ol std -t 1 modulator_map.ncd modulator.ncd modulator.pcfConstraints file: modulator.pcf.Loading device for application Rf_Device from file '3s200.nph' in environment D:\Xilinx.   "modulator" is an NCD, version 3.1, device xc3s200, package ft256, speed -4Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".Device speed data version:  "PRODUCTION 1.37 2005-11-04".Device Utilization Summary:   Number of BUFGMUXs                  1 out of 8      12%   Number of DCMs                      1 out of 4      25%   Number of External IOBs            55 out of 173    31%      Number of LOCed IOBs            55 out of 55    100%   Number of Slices                   73 out of 1920    3%      Number of SLICEMs                0 out of 960     0%Overall effort level (-ol):   Standard Placer effort level (-pl):    High Placer cost table entry (-t): 1Router effort level (-rl):    Standard WARNING:Par:288 - The signal ex_opt0_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_opt1_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<0>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<1>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<2>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<3>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<4>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_pms_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<5>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_opt_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<6>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal tp<7>_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_ppt_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_bds_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_pm_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal sdo_IBUF has no load.  PAR will not attempt to route this signal.WARNING:Par:288 - The signal ex_clk_IBUF has no load.  PAR will not attempt to route this signal.Starting PlacerPhase 1.1Phase 1.1 (Checksum:989904) REAL time: 5 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs Phase 3.2................Phase 3.2 (Checksum:98b53c) REAL time: 8 secs Phase 4.8.....................................................................................................................................Phase 4.8 (Checksum:9bafcf) REAL time: 8 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 8 secs Phase 6.18Phase 6.18 (Checksum:39386fa) REAL time: 9 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 9 secs Writing design to file modulator.ncdTotal REAL time to Placer completion: 9 secs Total CPU time to Placer completion: 8 secs Starting RouterPhase 1: 587 unrouted;       REAL time: 10 secs Phase 2: 530 unrouted;       REAL time: 10 secs Phase 3: 214 unrouted;       REAL time: 10 secs Phase 4: 214 unrouted; (2714)      REAL time: 10 secs Phase 5: 214 unrouted; (0)      REAL time: 10 secs Phase 6: 0 unrouted; (0)      REAL time: 10 secs Phase 7: 0 unrouted; (0)      REAL time: 10 secs Total REAL time to Router completion: 10 secs Total CPU time to Router completion: 9 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|                 clk |      BUFGMUX3| No   |   56 |  0.040     |  1.051      |+---------------------+--------------+------+------+------------+-------------+* Net Skew is the difference between the minimum and maximum routingonly delays for the net. Note this is different from Clock Skew whichis reported in TRCE timing report. Clock Skew is the difference betweenthe minimum and maximum path delays which includes logic delays.   The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        1.136   The MAXIMUM PIN DELAY IS:                               4.900   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.838   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------         316         164          24          39          12           0Timing Score: 0Asterisk (*) preceding a constraint indicates it was not met.   This may be due to a setup or hold violation.------------------------------------------------------------------------------------------------------  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of                                              |            |            | Levels | Slack      |errors     ------------------------------------------------------------------------------------------------------  Autotimespec constraint for clock net clk | N/A        | 5.965ns    | 2      | N/A        | N/A       ------------------------------------------------------------------------------------------------------All constraints were met.INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the   constraint does not cover any paths or that it has no requested value.Generating Pad Report.All signals are completely routed.WARNING:Par:284 - There are 17 sourceless or loadless signals in this design. This design will not pass the DRC check
   run by Bitgen.Total REAL time to PAR completion: 22 secs Total CPU time to PAR completion: 18 secs Peak Memory Usage:  123 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 18Number of info messages: 1Writing design to file modulator.ncdPAR done!