library verilog;use verilog.vl_types.all;entity ad9957_single is    generic(        CFG1            : string  := "cfr1";        CFG2            : string  := "cfr2";        CFG3            : string  := "cfr3";        AUX_DAC         : string  := "aux_dac";        IO_RATE         : string  := "ioupdate_rate";        SAF             : string  := "saf";        PRF0            : string  := "profile0";        PRF1            : string  := "profile1";        PRF2            : string  := "profile2";        PRF3            : string  := "profile3";        PRF4            : string  := "profile4";        PRF5            : string  := "profile5";        PRF6            : string  := "profile6";        PRF7            : string  := "profile7";        GPIO_C          : string  := "gpio_cfg";        GPIO_D          : string  := "gpio_dat";        \END\           : string  := "end";        DLY_CFG1        : string  := "dly_0";        DLY_CFG2        : string  := "dly_1";        DLY_CFG3        : string  := "dly_2";        DLY_AUX_DAC     : string  := "dly_3";        DLY_IO_RATE     : string  := "dly_4";        DLY_SAF         : string  := "dly_5";        DLY_PRF0        : string  := "dly_6";        IDLE            : string  := "idle";        SER0_PRE        : string  := "pre0";        SER0_START      : string  := "start0";        SER0_WAIT       : string  := "wait0";        SER0_END        : string  := "end0";        SER1_PRE        : string  := "pre1";        SER1_START      : string  := "start1";        SER1_WAIT       : string  := "wait1";        SER1_END        : string  := "end1";        SIG_END         : string  := "end"    );    port(        clk             : in     vl_logic;        nrst            : in     vl_logic;        start           : in     vl_logic;        ncs             : out    vl_logic;        sclk            : out    vl_logic;        sdio            : out    vl_logic;        sdo             : in     vl_logic;        io_update       : out    vl_logic;        io_reset        : out    vl_logic;        profile         : out    vl_logic_vector(2 downto 0);        end_single      : out    vl_logic    );end ad9957_single;