# BEGIN Project OptionsSET flowvendor = Foundation_iSESET vhdlsim = TrueSET verilogsim = TrueSET workingdirectory = E:\modulator\modulator_fpgaSET speedgrade = -4SET simulationfiles = BehavioralSET asysymbol = TrueSET addpads = FalseSET device = xc3s200SET implementationfiletype = EdifSET busformat = BusFormatAngleBracketNotRippedSET foundationsym = FalseSET package = ft256SET createndf = FalseSET designentry = VHDLSET devicefamily = spartan3SET formalverification = FalseSET removerpms = False# END Project Options# BEGIN SelectSELECT Single_Port_Block_Memory family Xilinx,_Inc. 6.2# END Select# BEGIN ParametersCSET handshaking_pins=falseCSET init_value=0CSET coefficient_file=E:\modulator\modulator_fpga\modulator\data.coeCSET select_primitive=16kx1CSET initialization_pin_polarity=Active_HighCSET global_init_value=0CSET depth=256CSET write_enable_polarity=Active_HighCSET port_configuration=Read_OnlyCSET enable_pin_polarity=Active_HighCSET component_name=sram_ctrlCSET active_clock_edge=Falling_Edge_TriggeredCSET disable_warning_messages=trueCSET additional_output_pipe_stages=0CSET limit_data_pitch=18CSET primitive_selection=Optimize_For_AreaCSET enable_pin=falseCSET init_pin=falseCSET write_mode=Read_After_WriteCSET has_limit_data_pitch=falseCSET load_init_file=trueCSET width=16CSET register_inputs=false# END ParametersGENERATE