Info (10151): Verilog HDL Declaration information at taxi.v(9): "flagmin" is declared here
Info: Found 1 design units, including 1 entities, in source file taxi.v
    Info: Found entity 1: taxi
Info: Elaborating entity "taxi" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at taxi.v(124): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at taxi.v(137): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at taxi.v(146): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(157): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(165): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(166): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(170): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(171): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(172): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(176): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(177): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(178): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(179): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(183): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(184): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(185): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(193): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(194): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(198): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(199): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(200): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(204): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(205): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(206): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(207): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(211): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(212): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(213): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(224): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(235): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(243): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(244): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(248): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(249): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(250): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(254): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(255): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(256): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(257): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(261): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(262): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(263): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(271): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(272): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(276): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(277): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(278): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(282): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(283): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(284): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(285): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(289): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(290): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at taxi.v(291): truncated value with size 32 to match size of target (4)
Info: Inferred 3 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "cha3[0]~549"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "km1[0]~48"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "min1[0]~48"
Info: Found 1 design units, including 1 entities, in source file c:/my software/quartus/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:cha3_rtl_0"
Info: Found 1 design units, including 1 entities, in source file c:/my software/quartus/quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "lpm_counter:cha3_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:cha3_rtl_0"
Info: Instantiated megafunction "lpm_counter:cha3_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Found 1 design units, including 1 entities, in source file c:/my software/quartus/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "lpm_add_sub:Add5"
Info: Found 1 design units, including 1 entities, in source file c:/my software/quartus/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add5"
Info: Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/my software/quartus/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add5"
Info: Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add5|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add5"
Info: Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/my software/quartus/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "lpm_add_sub:Add5|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add5"
Info: Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add5|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add5"
Info: Instantiated megafunction "lpm_add_sub:Add5" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info: Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Warning: Ignore assignments for "flagmile[0]" because it is an invalid assignment target -- "flagmile"  is a single bit, and cannot have members
Warning: Ignore assignments for "flagmile[1]" because it is an invalid assignment target -- "flagmile"  is a single bit, and cannot have members
Warning: Ignore assignments for "flagmin[0]" because it is an invalid assignment target -- "flagmin"  is a single bit, and cannot have members
Warning: Ignore assignments for "flagmin[1]" because it is an invalid assignment target -- "flagmin"  is a single bit, and cannot have members
Info: Implemented 178 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 34 output pins
    Info: Implemented 140 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 60 warnings
    Info: Allocated 136 megabytes of memory during processing
    Info: Processing ended: Fri Jul 06 14:03:33 2007
    Info: Elapsed time: 00:00:10