{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 06 14:03:50 2007 " "Info: Processing started: Fri Jul 06 14:03:50 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off taxi -c taxi --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off taxi -c taxi --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_PORT_DECL_WITH_DIMS" "flagmile packed taxi.v(5) " "Critical Warning (10226): Verilog HDL Port Declaration warning at taxi.v(5): port declaration for \"flagmile\" declares packed dimensions but the data type declaration does not" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 5 0 0 } }  } 1 10226 "Verilog HDL Port Declaration warning at %3!s!: port declaration for \"%1!s!\" declares %2!s! dimensions but the data type declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "flagmile taxi.v(9) " "Info (10151): Verilog HDL Declaration information at taxi.v(9): \"flagmile\" is declared here" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 9 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Critical Warning" "WVRFX_VERI_PORT_DECL_WITH_DIMS" "flagmin packed taxi.v(5) " "Critical Warning (10226): Verilog HDL Port Declaration warning at taxi.v(5): port declaration for \"flagmin\" declares packed dimensions but the data type declaration does not" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 5 0 0 } }  } 1 10226 "Verilog HDL Port Declaration warning at %3!s!: port declaration for \"%1!s!\" declares %2!s! dimensions but the data type declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "flagmin taxi.v(9) " "Info (10151): Verilog HDL Declaration information at taxi.v(9): \"flagmin\" is declared here" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 9 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "taxi.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file taxi.v" { { "Info" "ISGN_ENTITY_NAME" "1 taxi " "Info: Found entity 1: taxi" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "taxi " "Info: Elaborating entity \"taxi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 taxi.v(124) " "Warning (10230): Verilog HDL assignment warning at taxi.v(124): truncated value with size 32 to match size of target (8)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 taxi.v(137) " "Warning (10230): Verilog HDL assignment warning at taxi.v(137): truncated value with size 32 to match size of target (8)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(146) " "Warning (10230): Verilog HDL assignment warning at taxi.v(146): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(157) " "Warning (10230): Verilog HDL assignment warning at taxi.v(157): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(165) " "Warning (10230): Verilog HDL assignment warning at taxi.v(165): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(166) " "Warning (10230): Verilog HDL assignment warning at taxi.v(166): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(170) " "Warning (10230): Verilog HDL assignment warning at taxi.v(170): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 170 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(171) " "Warning (10230): Verilog HDL assignment warning at taxi.v(171): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 171 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(172) " "Warning (10230): Verilog HDL assignment warning at taxi.v(172): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 172 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(176) " "Warning (10230): Verilog HDL assignment warning at taxi.v(176): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 176 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(177) " "Warning (10230): Verilog HDL assignment warning at taxi.v(177): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 177 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(178) " "Warning (10230): Verilog HDL assignment warning at taxi.v(178): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 178 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(179) " "Warning (10230): Verilog HDL assignment warning at taxi.v(179): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 179 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(183) " "Warning (10230): Verilog HDL assignment warning at taxi.v(183): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(184) " "Warning (10230): Verilog HDL assignment warning at taxi.v(184): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 184 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 taxi.v(185) " "Warning (10230): Verilog HDL assignment warning at taxi.v(185): truncated value with size 32 to match size of target (4)" {  } { { "taxi.v" "" { Text "F:/study/course/課程設計/my taxi/taxi.v" 185 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}